Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-sof

qemu-riscv

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Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-sof

From:	Richard Henderson
Subject:	Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles
Date:	Wed, 20 Oct 2021 07:57:38 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/19/21 2:47 AM, Frédéric Pétrot wrote:

This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. Most of these modifications have to deal
with changing what was a binary choice into a ternary one.  Although we did
our best to avoid testing for TARGET_RISCV128 (which we did), it is
implicitly there in '#else' statements.
Most added infrastructure files are no far from being copies of the 64-bit
version.
Once this patch applied, adding risc128-sofmmu to --target-list produces
a (no so useful yet) executable.

Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
---
  configs/devices/riscv128-softmmu/default.mak | 17 +++++++
  configs/targets/riscv128-softmmu.mak         |  6 +++
  include/disas/dis-asm.h                      |  1 +
  include/hw/riscv/sifive_cpu.h                |  3 ++
  target/riscv/cpu-param.h                     |  5 ++
  target/riscv/cpu.h                           |  3 ++
  disas/riscv.c                                |  5 ++
  target/riscv/cpu.c                           | 23 +++++++++-
  target/riscv/gdbstub.c                       |  3 ++
  target/riscv/insn_trans/trans_rvd.c.inc      | 12 ++---
  target/riscv/insn_trans/trans_rvf.c.inc      |  6 +--
  gdb-xml/riscv-128bit-cpu.xml                 | 48 ++++++++++++++++++++
  gdb-xml/riscv-128bit-virtual.xml             | 12 +++++
  target/riscv/Kconfig                         |  3 ++
  14 files changed, 137 insertions(+), 10 deletions(-)
  create mode 100644 configs/devices/riscv128-softmmu/default.mak
  create mode 100644 configs/targets/riscv128-softmmu.mak
  create mode 100644 gdb-xml/riscv-128bit-cpu.xml
  create mode 100644 gdb-xml/riscv-128bit-virtual.xml

So... do we really want to go down this route, with a separate binary? It seems like wecould reasonably support rv128 in the qemu-system-riscv64 binary with -cpu rv128.

+++ b/gdb-xml/riscv-128bit-cpu.xml
@@ -0,0 +1,48 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- FIXME : All GPRs are marked as 64-bits since gdb doesn't like 128-bit 
registers for now. -->


If the widths are not correct, we can just as easily skip it for now.


r~

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Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, (continued)
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Richard Henderson, 2021/10/20
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/20
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 01/21] memory: change define name for consistency, Philippe Mathieu-Daudé, 2021/10/20
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Richard Henderson, 2021/10/20
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson <=
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Richard Henderson, 2021/10/20
- [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Richard Henderson, 2021/10/20
- [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/10/20
    - Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/20
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Richard Henderson, 2021/10/20
- [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/19

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