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[PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN
From: |
LIU Zhiwei |
Subject: |
[PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN |
Date: |
Thu, 11 Nov 2021 23:51:31 +0800 |
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..a6a73ced9e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
}
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+ if (get_xl(ctx) == MXL_RV32) {
+ dest = (int32_t)dest;
+ }
+ tcg_gen_movi_tl(cpu_pc, dest);
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_exception_mtval(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
@@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n,
target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_lookup_and_goto_ptr();
}
}
--
2.25.1
- [PATCH v4 00/20] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/11
- [PATCH v4 01/20] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/11
- [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN,
LIU Zhiwei <=
- [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/11
- [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/11
- [PATCH v4 06/20] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/11
- [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/11