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[PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl |
Date: |
Thu, 25 Nov 2021 15:39:30 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 12 ++++--------
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..ce20c3a970 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1407,9 +1407,22 @@ static RISCVException write_mseccfg(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
+{
+ if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
+ return false;
+ }
+ return true;
+}
+
static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
+ uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+ if (!check_pmp_reg_index(env, reg_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
*val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
return RISCV_EXCP_NONE;
}
@@ -1417,6 +1430,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env,
int csrno,
static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
+ uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+ if (!check_pmp_reg_index(env, reg_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 54abf42583..81b61bb65c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
reg_index,
{
int i;
uint8_t cfg_val;
+ int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
- if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
- qemu_log_mask(LOG_GUEST_ERROR,
- "ignoring pmpcfg write - incorrect address\n");
- return;
- }
-
- for (i = 0; i < sizeof(target_ulong); i++) {
+ for (i = 0; i < pmpcfg_nums; i++) {
cfg_val = (val >> 8 * i) & 0xff;
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
}
@@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t
reg_index)
int i;
target_ulong cfg_val = 0;
target_ulong val = 0;
+ int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
- for (i = 0; i < sizeof(target_ulong); i++) {
+ for (i = 0; i < pmpcfg_nums; i++) {
val = pmp_read_cfg(env, (reg_index * 4) + i);
cfg_val |= (val << (i * 8));
}
--
2.25.1
- [PATCH v5 00/22] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/25
- [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl,
LIU Zhiwei <=
- [PATCH v5 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/25
- [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 04/22] target/riscv: Create xl field in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/25
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/25
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25