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[PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN
From: |
LIU Zhiwei |
Subject: |
[PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN |
Date: |
Thu, 13 Jan 2022 19:39:58 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +++++
target/riscv/vector_helper.c | 7 +++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index abf217e34f..645a1b3f6c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -478,6 +478,11 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
}
#endif
+static inline int riscv_cpu_xlen(CPURISCVState *env)
+{
+ return 16 << env->xl;
+}
+
/*
* Encode LMUL to lmul as follows:
* LMUL vlmul lmul
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a9484c22ea..8b7c9ec890 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -36,8 +36,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong
s1,
uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
- bool vill = FIELD_EX64(s2, VTYPE, VILL);
- target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+ int xlen = riscv_cpu_xlen(env);
+ bool vill = (s2 >> (xlen - 1)) & 0x1;
+ target_ulong reserved = s2 &
+ MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if (lmul & 4) {
/* Fractional LMUL. */
--
2.25.1
- [PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN, (continued)
- [PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2022/01/13
- [PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/13
- [PATCH v6 09/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/13
- [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/13
- [PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/13
- [PATCH v6 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/13
- [PATCH v6 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/13
- [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN,
LIU Zhiwei <=
- [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/13
- [PATCH v6 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/13
- [PATCH v6 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/13
- [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/13
- [PATCH v6 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/13