[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu
From: |
Atish Patra |
Subject: |
[PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu |
Date: |
Fri, 18 Feb 2022 16:25:09 -0800 |
From: Atish Patra <atish.patra@wdc.com>
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 09dc07d12d6f..173b9d3c5d3e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -768,7 +768,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5d914bd34550..2dc491887f24 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -365,7 +365,7 @@ struct RISCVCPUConfig {
bool ext_zbb;
bool ext_zbc;
bool ext_zbs;
- bool ext_counters;
+ bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
bool ext_svinval;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 789f0c598932..2c3bba81c8af 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -69,8 +69,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
- if (!cpu->cfg.ext_counters) {
- /* The Counters extensions is not enabled */
+ if (!cpu->cfg.ext_pmu) {
+ /* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.30.2
- [PATCH v5 00/12] Improve PMU support, Atish Patra, 2022/02/18
- [PATCH v5 00/12] Improve PMU support, Atish Patra, 2022/02/18
- [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/02/18
- [PATCH v5 02/12] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/02/18
- [PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu,
Atish Patra <=
- [PATCH v5 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/02/18
- [PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/02/18
- [PATCH v5 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/02/18
- [PATCH v5 09/12] target/riscv: Simplify counter predicate function, Atish Patra, 2022/02/18
- [PATCH v5 10/12] target/riscv: Add few cache related PMU events, Atish Patra, 2022/02/18
- [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/02/18
- [PATCH v5 12/12] target/riscv: Update the privilege field for sscofpmf CSRs, Atish Patra, 2022/02/18
- [PATCH v5 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/02/18
- [PATCH v5 11/12] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2022/02/18