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[PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR
From: |
Atish Patra |
Subject: |
[PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR |
Date: |
Fri, 18 Feb 2022 16:25:11 -0800 |
From: Atish Patra <atish.patra@wdc.com>
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 4 ++++
target/riscv/csr.c | 25 +++++++++++++++++++++++++
target/riscv/machine.c | 1 +
4 files changed, 32 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f6b994a74ed9..ea3862ccbf5c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -259,6 +259,8 @@ struct CPURISCVState {
target_ulong scounteren;
target_ulong mcounteren;
+ target_ulong mcountinhibit;
+
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bb47cf7e77a2..48b39e6d52a7 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -367,6 +367,10 @@
#define CSR_MHPMCOUNTER29 0xb1d
#define CSR_MHPMCOUNTER30 0xb1e
#define CSR_MHPMCOUNTER31 0xb1f
+
+/* Machine counter-inhibit register */
+#define CSR_MCOUNTINHIBIT 0x320
+
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d69bd2d88454..2283ff33a5d7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1379,6 +1379,28 @@ static RISCVException write_mtvec(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ *val = env->mcountinhibit;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ env->mcountinhibit = val;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3553,6 +3575,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
+ write_mcountinhibit },
+
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ebc33c9e2781..a34cc3f69c4b 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -299,6 +299,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.siselect, RISCVCPU),
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
--
2.30.2
- [PATCH v5 00/12] Improve PMU support, Atish Patra, 2022/02/18
- [PATCH v5 00/12] Improve PMU support, Atish Patra, 2022/02/18
- [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/02/18
- [PATCH v5 02/12] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/02/18
- [PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2022/02/18
- [PATCH v5 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/02/18
- [PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR,
Atish Patra <=
- [PATCH v5 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/02/18
- [PATCH v5 09/12] target/riscv: Simplify counter predicate function, Atish Patra, 2022/02/18
- [PATCH v5 10/12] target/riscv: Add few cache related PMU events, Atish Patra, 2022/02/18
- [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/02/18
- [PATCH v5 12/12] target/riscv: Update the privilege field for sscofpmf CSRs, Atish Patra, 2022/02/18
- [PATCH v5 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/02/18
- [PATCH v5 11/12] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2022/02/18