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[PATCH 3/5] hw/riscv: virt: Fix the plic's address cells
From: |
Conor Dooley |
Subject: |
[PATCH 3/5] hw/riscv: virt: Fix the plic's address cells |
Date: |
Fri, 5 Aug 2022 16:54:03 +0100 |
From: Conor Dooley <conor.dooley@microchip.com>
When optional AIA PLIC support was added the to the virt machine, the
address cells property was removed leading the issues with dt-validate
on a dump from the virt machine:
/stuff/qemu/qemu.dtb: plic@c000000: '#address-cells' is a required property
From schema:
/stuff/linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Add back the property to suppress the warning.
Reported-by: Rob Herring <robh@kernel.org>
Link:
https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Fixes: e6faee6585 ("hw/riscv: virt: Add optional AIA APLIC support to virt
machine")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
hw/riscv/virt.c | 2 ++
include/hw/riscv/virt.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6c61a406c4..8b2978076e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -465,6 +465,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
qemu_fdt_add_subnode(mc->fdt, plic_name);
qemu_fdt_setprop_cell(mc->fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ "#address-cells", FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
(char **)&plic_compat,
ARRAY_SIZE(plic_compat));
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 984e55c77f..be4ab8fe7f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -111,6 +111,7 @@ enum {
#define FDT_PCI_ADDR_CELLS 3
#define FDT_PCI_INT_CELLS 1
+#define FDT_PLIC_ADDR_CELLS 0
#define FDT_PLIC_INT_CELLS 1
#define FDT_APLIC_INT_CELLS 2
#define FDT_IMSIC_INT_CELLS 0
--
2.37.1
- Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings, (continued)
[PATCH 2/5] hw/riscv: virt: fix uart node name, Conor Dooley, 2022/08/05
[PATCH 4/5] hw/riscv: virt: fix syscon subnode paths, Conor Dooley, 2022/08/05
[PATCH 5/5] hw/core: fix platform bus node name, Conor Dooley, 2022/08/05
[PATCH 3/5] hw/riscv: virt: Fix the plic's address cells,
Conor Dooley <=