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Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting
Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings
Tue, 9 Aug 2022 06:51:52 +1000
On Tue, Aug 9, 2022 at 2:14 AM <Conor.Dooley@microchip.com> wrote:
> On 08/08/2022 16:03, Tsukasa OI wrote:
> > I agree with Alistair. **I** removed 'S' and 'U' from the ISA string
> > and it should be working in the latest development branch (I tested).
> Yeah, I saw what you as I looked at the commit log while trying to
> understand why there were invalid strings appearing when the code
> looked like it was impossible. Certainly I found it very very odd.
> I didn't just revive a 2 year old patch without taking a look at
> the code.
> > Besides, this function alone generates the ISA string for DTB and
> > there's no way such ISA strings with invalid 'S' and 'U' can be
> > generated. It's definitely a behavior of QEMU 7.0 or before.
> Hmm, it would seem that you're right - I have retested on a fresh
> clone. I did checkout v7.1.0-rc1 before running the first build that
> I saw the invalid string on as I'd been on some hacked up & fossilised
> version prior to that. Perhaps some build artifacts were not correctly
> removed, consider me quite confused! I do recall the configure script
> saying something about my build directory when I kicked it off, so
> it is likely down to that.
> Unfortunately my bash history is out of order so I will not be able to
> replicate the conditions, having many terminals open does have it's
> > Please. Please make sure that you are testing the right version of QEMU.
> Heh. Please, please give me some allowance for reasonably believing I
> was in fact on the latest qemu/master after checking it out and building!
No worries! Glad we cleared that up
> I guess this patch can then be safely ignored :)
> Glad to have cleared this up as I was rather confused by what I saw.
Great! Do you mind resending the series then with this patch dropped?
It just makes it easier for me to track and manage
> Thanks Tsukasa/Alistair.
[PATCH 2/5] hw/riscv: virt: fix uart node name, Conor Dooley, 2022/08/05
[PATCH 4/5] hw/riscv: virt: fix syscon subnode paths, Conor Dooley, 2022/08/05
[PATCH 5/5] hw/core: fix platform bus node name, Conor Dooley, 2022/08/05
[PATCH 3/5] hw/riscv: virt: Fix the plic's address cells, Conor Dooley, 2022/08/05