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[PULL 0/9] Fourth RISC-V PR for QEMU 8.0

From: Palmer Dabbelt
Subject: [PULL 0/9] Fourth RISC-V PR for QEMU 8.0
Date: Fri, 17 Feb 2023 09:51:54 -0800

The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:

  tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09 
11:23:53 +0000)

are available in the Git repository at:

  https://github.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230217

for you to fetch changes up to e8c0697d79ef05aa5aefb1121dfede59855556b4:

  target/riscv: Fix vslide1up.vf and vslide1down.vf (2023-02-16 08:10:40 -0800)

Fourth RISC-V PR for QEMU 8.0

* A triplet of cleanups to the kernel/initrd loader that avoids
  duplication between the various boards.
* OpenSBI has been updated to version 1.2.
* Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as
  reviewers.  Thanks for the help!
* A fix for PMP matching to avoid incorrectly appling the default
  permissions on PMP permission violations.
* A cleanup to avoid an unnecessary avoid env_archcpu() in
* Fixes for the vector slide instructions to avoid truncating 64-bit
  values (such as doubles) on 32-bit targets.

Alistair is going to be out for a bit, so I'm going to pick up the pull
requests for a bit until he's back online.  It's been a while so
apologies in advance if anything has gone off the rails, the only thing
I know of is that I moved to a Yubikey a while ago so there's likely
some new subkeys involved in the signing here.

This is all passing my standard tests (make check along with a handful
of Linux boots), both on its own and when merge into master from this
morning.  There has been some flakiness in both of those for a while
now, but it doesn't appear to be anything new here (and I think might
just be flaky infrastructure on my end).

Alistair Francis (1):
      MAINTAINERS: Add some RISC-V reviewers

Bin Meng (1):
      roms/opensbi: Upgrade from v1.1 to v1.2

Daniel Henrique Barboza (4):
      hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
      hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
      hw/riscv/boot.c: make riscv_load_initrd() static
      target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()

Frank Chang (1):
      target/riscv: Remove privileged spec version restriction for RVV

Himanshu Chauhan (1):
      target/riscv: Smepmp: Skip applying default rules when address matches

LIU Zhiwei (1):
      target/riscv: Fix vslide1up.vf and vslide1down.vf

 MAINTAINERS                                    |   3 +
 hw/riscv/boot.c                                |  97 ++++++++++++++++---------
 hw/riscv/microchip_pfsoc.c                     |  12 +--
 hw/riscv/opentitan.c                           |   4 +-
 hw/riscv/sifive_e.c                            |   4 +-
 hw/riscv/sifive_u.c                            |  12 +--
 hw/riscv/spike.c                               |  14 +---
 hw/riscv/virt.c                                |  12 +--
 include/hw/riscv/boot.h                        |   3 +-
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 117704 -> 123072 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 115344 -> 121800 bytes
 roms/opensbi                                   |   2 +-
 target/riscv/cpu.c                             |   2 +-
 target/riscv/cpu_helper.c                      |   2 +-
 target/riscv/csr.c                             |  21 ++----
 target/riscv/pmp.c                             |   9 ++-
 target/riscv/vector_helper.c                   |   4 +-
 17 files changed, 99 insertions(+), 102 deletions(-)

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