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[PULL 9/9] target/riscv: Fix vslide1up.vf and vslide1down.vf
From: |
Palmer Dabbelt |
Subject: |
[PULL 9/9] target/riscv: Fix vslide1up.vf and vslide1down.vf |
Date: |
Fri, 17 Feb 2023 09:52:03 -0800 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these instructions on qemu-riscv32.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230213094550.29621-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 00de879787..3073c54871 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
-static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
+static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
@@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
-static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
+static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
--
2.39.0
- [PULL 0/9] Fourth RISC-V PR for QEMU 8.0, Palmer Dabbelt, 2023/02/17
- [PULL 2/9] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel(), Palmer Dabbelt, 2023/02/17
- [PULL 1/9] hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel(), Palmer Dabbelt, 2023/02/17
- [PULL 3/9] hw/riscv/boot.c: make riscv_load_initrd() static, Palmer Dabbelt, 2023/02/17
- [PULL 5/9] target/riscv: Remove privileged spec version restriction for RVV, Palmer Dabbelt, 2023/02/17
- [PULL 6/9] MAINTAINERS: Add some RISC-V reviewers, Palmer Dabbelt, 2023/02/17
- [PULL 7/9] target/riscv: Smepmp: Skip applying default rules when address matches, Palmer Dabbelt, 2023/02/17
- [PULL 8/9] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state(), Palmer Dabbelt, 2023/02/17
- [PULL 4/9] roms/opensbi: Upgrade from v1.1 to v1.2, Palmer Dabbelt, 2023/02/17
- [PULL 9/9] target/riscv: Fix vslide1up.vf and vslide1down.vf,
Palmer Dabbelt <=
- Re: [PULL 0/9] Fourth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/02/21