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[PATCH v1 00/20] s390x/tcg: Implement Vector enhancements facility and s
From: |
David Hildenbrand |
Subject: |
[PATCH v1 00/20] s390x/tcg: Implement Vector enhancements facility and switch to z14 |
Date: |
Wed, 30 Sep 2020 16:55:03 +0200 |
This series adds support for the "Vector enhancements facility" and bumps
the qemu CPU model tp to a stripped-down z14.
I yet have to find a way to get more test coverage - looks like some of
the functions aren't used anywhere yet (e.g., VECTOR FP MAXIMUM), writing
unit tests to cover all functions and cases is just nasty. But I might be
wrong - I'm planning to at least test basic functionality of all new added
instructions.
I have to make excessive use of c macros again to cover different element
sizes (32/64/128bit). Any advise to clean things up are welcome.
This is based on:
"[PATCH v2 0/9] s390x/tcg: Implement some z14 facilities"
"[PATCH v2 00/10] softfloat: Implement float128_muladd"
Based-on: 20200928122717.30586-1-david@redhat.com
Based-on: 20200925152047.709901-1-richard.henderson@linaro.org
David Hildenbrand (20):
softfloat: Implement
float128_(min|minnum|minnummag|max|maxnum|maxnummag)
s390x/tcg: Implement VECTOR BIT PERMUTE
s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL
s390x/tcg: Implement 32/128 bit for VECTOR FP ADD
s390x/tcg: Implement 32/128 bit for VECTOR FP DIVIDE
s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY
s390x/tcg: Implement 32/128 bit for VECTOR FP SUBTRACT
s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL)
SCALAR
s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *
s390x/tcg: Implement 32/128 bit for VECTOR LOAD FP INTEGER
s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED
s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED
s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION
s390x/tcg: Implement 32/128 bit for VECTOR FP SQUARE ROOT
s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS
IMMEDIATE
s390x/tcg: Implement 32/128bit for VECTOR FP MULTIPLY AND
(ADD|SUBTRACT)
s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)
s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)
s390x/tcg: We support Vector enhancements facility
s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2
fpu/softfloat.c | 100 +++
hw/s390x/s390-virtio-ccw.c | 2 +
include/fpu/softfloat.h | 6 +
target/s390x/cpu_models.c | 4 +-
target/s390x/gen-features.c | 14 +-
target/s390x/helper.h | 72 ++
target/s390x/insn-data.def | 12 +
target/s390x/translate_vx.c.inc | 625 ++++++++++++---
target/s390x/vec_fpu_helper.c | 1302 ++++++++++++++++++++++---------
target/s390x/vec_helper.c | 22 +
10 files changed, 1681 insertions(+), 478 deletions(-)
--
2.26.2
- [PATCH v1 00/20] s390x/tcg: Implement Vector enhancements facility and switch to z14,
David Hildenbrand <=
- [PATCH v1 01/20] softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag), David Hildenbrand, 2020/09/30
- [PATCH v1 03/20] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL, David Hildenbrand, 2020/09/30
- [PATCH v1 05/20] s390x/tcg: Implement 32/128 bit for VECTOR FP DIVIDE, David Hildenbrand, 2020/09/30
- [PATCH v1 02/20] s390x/tcg: Implement VECTOR BIT PERMUTE, David Hildenbrand, 2020/09/30
- [PATCH v1 04/20] s390x/tcg: Implement 32/128 bit for VECTOR FP ADD, David Hildenbrand, 2020/09/30
- [PATCH v1 06/20] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY, David Hildenbrand, 2020/09/30
- [PATCH v1 08/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, David Hildenbrand, 2020/09/30
- [PATCH v1 07/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SUBTRACT, David Hildenbrand, 2020/09/30
- [PATCH v1 10/20] s390x/tcg: Implement 32/128 bit for VECTOR LOAD FP INTEGER, David Hildenbrand, 2020/09/30