Re: [Simulavr-devel] Trouble building master branch

[Raphaël Martin]

> And yet another way would be to use the verilog interface and connect  
> your AVRs in Verilog. If you have other surrounding logic, this can also  
> be modeled. In the examples/verilog directory, there is an example of  
> software based single-pin protocol (thus even covering bidirectional PIN  
> usage from verilog). The verilog doesn't consist of so much more than  
> connecting two devices and starting the simulation, so it is somewhat  
> similar to your case.
>

Yes I had noticed that you added verilog support in master branch. Read
documentation about that and it looks damn interesting for testing
purposes !
Thanks for the tip Onno, I'll check tat samples

-- 
Raphaël
.
Linus Torvalds first written program had artificial intelligence.
-- Linus Torvalds facts