Re: [Lightning] Porting GNU Smalltalk to lightning 2

[Holger Hans Peter Freyther]

On Wed, Nov 19, 2014 at 12:00:48AM -0200, Paulo César Pereira de Andrade wrote:

> $ cat /proc/cpuinfo

processor       : 0
model name      : ARM926EJ-S rev 5 (v5l)
BogoMIPS        : 201.11
Features        : swp half thumb fastmult edsp java 
CPU implementer : 0x41
CPU architecture: 5TEJ
CPU variant     : 0x0
CPU part        : 0x926
CPU revision    : 4


> > ~/lightning/build/check# .libs/ccall -h
> > Illegal instruction
> 
> please also run:
> 
> $ cd check
> $ make debug
> [...]
> (gdb) b _jit_clear_state
> (gdb) r 3to2.tst
> (gdb) x/80i _jit->code.ptr
> (gdb) c
> <<< it crashes >>>
> (gdb) x/10i $pc-20
> 
> But I am almost sure it is caused by the macro
> 
> #  define jit_armv5e_p()        (jit_cpu.version >= 5 && jit_cpu.extend)


right. ldrd doesn't seem to be available[1] at the same time they claim
it is[2]

(gdb) x/80i _jit->code.ptr
   0xb6eb8000:  b       0xb6eb84d8
   0xb6eb8004:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
   0xb6eb8008:  mov     r11, sp
   0xb6eb800c:  sub     sp, sp, #72     ; 0x48
   0xb6eb8010:  ldrd    r11, [r2]
   0xb6eb8014:  strd    r2, [r11, #-8]
   0xb6eb8018:  ldrd    r11, [r2, #8]
   0xb6eb801c:  strd    r2, [r11, #-8]
   0xb6eb8020:  str     r0, [r11, #-68] ; 0x44
   0xb6eb8024:  ldrd    r0, [r11, #-8]
   0xb6eb8028:  ldrd    r2, [r11, #-8]
   0xb6eb802c:  ldr     r12, [pc, #28]  ; 0xb6eb8050
   0xb6eb8030:  blx     r12
   0xb6eb8034:  strd    r0, [r11, #-8]
   0xb6eb8038:  ldr     r0, [r11, #-68] ; 0x44
   0xb6eb803c:  ldrd    r2, [r11, #-8]
   0xb6eb8040:  mov     r0, r2
   0xb6eb8044:  mov     r1, r3
   0xb6eb8048:  add     sp, r11, #16
   0xb6eb804c:  pop     {r4, r5, r6, r7, r8, r9, r11, pc}
   0xb6eb8050:  usatlt  r0, #31, r8, asr #15
   0xb6eb8054:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
   0xb6eb8058:  mov     r11, sp
---Type <return> to continue, or q <return> to quit---
   0xb6eb805c:  sub     sp, sp, #72     ; 0x48
   0xb6eb8060:  ldrd    r11, [r2]
   0xb6eb8064:  strd    r2, [r11, #-8]
   0xb6eb8068:  ldrd    r11, [r2, #8]
   0xb6eb806c:  strd    r2, [r11, #-16]
   0xb6eb8070:  str     r0, [r11, #-68] ; 0x44
   0xb6eb8074:  ldrd    r0, [r11, #-8]
   0xb6eb8078:  ldrd    r2, [r11, #-16]
   0xb6eb807c:  ldr     r12, [pc, #-52] ; 0xb6eb8050
   0xb6eb8080:  blx     r12
   0xb6eb8084:  strd    r0, [r11, #-8]
   0xb6eb8088:  ldr     r0, [r11, #-68] ; 0x44
   0xb6eb808c:  ldrd    r2, [r11, #-8]
   0xb6eb8090:  mov     r0, r2
   0xb6eb8094:  mov     r1, r3
   0xb6eb8098:  add     sp, r11, #16
   0xb6eb809c:  pop     {r4, r5, r6, r7, r8, r9, r11, pc}
   0xb6eb80a0:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
   0xb6eb80a4:  mov     r11, sp
   0xb6eb80a8:  sub     sp, sp, #72     ; 0x48
   0xb6eb80ac:  ldrd    r11, [r2]
   0xb6eb80b0:  strd    r2, [r11, #-16]
   0xb6eb80b4:  ldrd    r11, [r2, #8]
---Type <return> to continue, or q <return> to quit---
   0xb6eb80b8:  strd    r2, [r11, #-8]
   0xb6eb80bc:  str     r0, [r11, #-68] ; 0x44
   0xb6eb80c0:  ldrd    r0, [r11, #-16]
   0xb6eb80c4:  ldrd    r2, [r11, #-8]
   0xb6eb80c8:  ldr     r12, [pc, #-128]        ; 0xb6eb8050
   0xb6eb80cc:  blx     r12
   0xb6eb80d0:  strd    r0, [r11, #-8]
   0xb6eb80d4:  ldr     r0, [r11, #-68] ; 0x44
   0xb6eb80d8:  ldrd    r2, [r11, #-8]
   0xb6eb80dc:  mov     r0, r2
   0xb6eb80e0:  mov     r1, r3
   0xb6eb80e4:  add     sp, r11, #16
   0xb6eb80e8:  pop     {r4, r5, r6, r7, r8, r9, r11, pc}
   0xb6eb80ec:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
   0xb6eb80f0:  mov     r11, sp
   0xb6eb80f4:  sub     sp, sp, #72     ; 0x48
   0xb6eb80f8:  ldrd    r11, [r2]
   0xb6eb80fc:  strd    r2, [r11, #-16]
   0xb6eb8100:  ldrd    r11, [r2, #8]
   0xb6eb8104:  strd    r2, [r11, #-24] ; 0xffffffe8
   0xb6eb8108:  str     r0, [r11, #-68] ; 0x44
   0xb6eb810c:  ldrd    r0, [r11, #-16]
   0xb6eb8110:  ldrd    r2, [r11, #-24] ; 0xffffffe8
---Type <return> to continue, or q <return> to quit---
   0xb6eb8114:  ldr     r12, [pc, #-204]        ; 0xb6eb8050
   0xb6eb8118:  blx     r12
   0xb6eb811c:  strd    r0, [r11, #-8]
   0xb6eb8120:  ldr     r0, [r11, #-68] ; 0x44
   0xb6eb8124:  ldrd    r2, [r11, #-8]
   0xb6eb8128:  mov     r0, r2
   0xb6eb812c:  mov     r1, r3
   0xb6eb8130:  add     sp, r11, #16
   0xb6eb8134:  pop     {r4, r5, r6, r7, r8, r9, r11, pc}
   0xb6eb8138:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
   0xb6eb813c:  mov     r11, sp
(gdb) c
Continuing.

Program received signal SIGILL, Illegal instruction.
0xb6eb8010 in ?? ()
(gdb)  x/10i $pc-20
   0xb6eb7ffc:  Cannot access memory at address 0xb6eb7ffc
(gdb)  x/10i $pc-16
   0xb6eb8000:  b       0xb6eb84d8
   0xb6eb8004:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
   0xb6eb8008:  mov     r11, sp
   0xb6eb800c:  sub     sp, sp, #72     ; 0x48
=> 0xb6eb8010:  ldrd    r11, [r2]
   0xb6eb8014:  strd    r2, [r11, #-8]
   0xb6eb8018:  ldrd    r11, [r2, #8]
   0xb6eb801c:  strd    r2, [r11, #-8]
   0xb6eb8020:  str     r0, [r11, #-68] ; 0x44
   0xb6eb8024:  ldrd    r0, [r11, #-8]

r0             0x0      0
r1             0x40080000       1074266112
r2             0x0      0
r3             0x40000000       1073741824
r4             0xbefffd84       3204447620
r5             0x1      1
r6             0xb6eb8000       3068887040
r7             0x26a20  158240
r8             0x0      0
r9             0x24a28  150056
r10            0x26a20  158240
r11            0xbeffdb50       3204438864
r12            0xb6eb8004       3068887044
sp             0xbeffdb08       0xbeffdb08
lr             0xb6eb84fc       3068888316
pc             0xb6eb8010       0xb6eb8010
cpsr           0x60000010       1610612752


After a quick read the issue seems that the register should
be even and not odd. Is this constraint not honored here? The
sad news is that even if I force armv4 gst will segfault. I
will need to figure out where but will not have time for that
until the weekend.

kind regards
        holger



[1] 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dvi0018b/ar01s02.html
[2] 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/BABJCGCF.html