Re: [Lightning] Porting GNU Smalltalk to lightning 2

[Paulo César Pereira de Andrade]

2014-11-19 7:39 GMT-02:00 Holger Hans Peter Freyther <address@hidden>:
> On Wed, Nov 19, 2014 at 12:00:48AM -0200, Paulo César Pereira de Andrade 
> wrote:
>
>> $ cat /proc/cpuinfo
>
> processor       : 0
> model name      : ARM926EJ-S rev 5 (v5l)
> BogoMIPS        : 201.11
> Features        : swp half thumb fastmult edsp java
> CPU implementer : 0x41
> CPU architecture: 5TEJ
> CPU variant     : 0x0
> CPU part        : 0x926
> CPU revision    : 4

> Program received signal SIGILL, Illegal instruction.
> 0xb6eb8010 in ?? ()
> (gdb)  x/10i $pc-20
>    0xb6eb7ffc:  Cannot access memory at address 0xb6eb7ffc
> (gdb)  x/10i $pc-16
>    0xb6eb8000:  b       0xb6eb84d8
>    0xb6eb8004:  push    {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r11, lr}
>    0xb6eb8008:  mov     r11, sp
>    0xb6eb800c:  sub     sp, sp, #72     ; 0x48
> => 0xb6eb8010:  ldrd    r11, [r2]

I messed something really bad at some point.
The registers are reversed, r11 is the frame pointer.
This should correct it:

---%<---
diff --git a/lib/jit_arm-cpu.c b/lib/jit_arm-cpu.c
index 552bce3..ec62642 100644
--- a/lib/jit_arm-cpu.c
+++ b/lib/jit_arm-cpu.c
@@ -711,7 +711,7 @@ static void _torl(jit_state_t*,int,int,int) maybe_unused;
 #  define CC_LDRDN(cc,rt,rn,rm)                corrr(cc,ARM_LDRD,rn,rt,rm)
 #  define LDRDN(rd,rn,rm)              CC_LDRDN(ARM_CC_AL,rn,rt,rm)
 #  define CC_LDRDI(cc,rt,rn,im)
corri8(cc,ARM_LDRDI|ARM_P,rn,rt,im)
-#  define LDRDI(rt,rn,im)              CC_LDRDI(ARM_CC_AL,rn,rt,im)
+#  define LDRDI(rt,rn,im)              CC_LDRDI(ARM_CC_AL,rt,rn,im)
 #  define CC_LDRDIN(cc,rt,rn,im)       corri8(cc,ARM_LDRDI,rn,rt,im)
 #  define LDRDIN(rt,rn,im)             CC_LDRDIN(ARM_CC_AL,rt,rn,im)
 #  define T2_LDRDIN(rt,rt2,rn,im)      torrri8(THUMB2_LDRDI,rn,rt,rt2,im)
---%<---

>    0xb6eb8014:  strd    r2, [r11, #-8]
>    0xb6eb8018:  ldrd    r11, [r2, #8]
>    0xb6eb801c:  strd    r2, [r11, #-8]
>    0xb6eb8020:  str     r0, [r11, #-68] ; 0x44
>    0xb6eb8024:  ldrd    r0, [r11, #-8]

> After a quick read the issue seems that the register should
> be even and not odd. Is this constraint not honored here? The
> sad news is that even if I force armv4 gst will segfault. I
> will need to figure out where but will not have time for that
> until the weekend.

  I will make a proper commit before the week end (maybe later today),
adding a check to ensure alternate code paths (the ones were it is not
guaranteed even) do not use ldrd/strd if the first register (in the register
pair) is odd.

> kind regards
>         holger
>
>
>
> [1] 
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dvi0018b/ar01s02.html
> [2] 
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/BABJCGCF.html

Thanks,
Paulo