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From: | Jochen Strohbeck |
Subject: | Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled |
Date: | Sun, 03 Dec 2017 09:06:00 +0000 |
As a quick test I placed descriptors and the entire pool into non-cacheable SRAM. No further code changes are necessary although it took some time tweaking the linker and lwipopts.h file. I had to shrink it a little to fit into a 64kB section but network communication still seems to be stable. Could this be a solution in order to run uC with cache enabled while keeping lwip code 'almost as is' ? Following your posts I feel a little overloaded by your input - "zero copy" etc. I understand that I have to do some RTFM and spend some time in the mailing list in order to do something that makes _really_ sense. The next step would be to upgrade to 2.0.3 I guess. Jochen
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