Re: [Qemu-devel] [PATCH] target-mips: Enable access to required RDHWR hardware registers

[Meador Inge]

On 08/21/2012 10:52 AM, Aurelien Jarno wrote:

> Le 21/08/2012 17:41, Meador Inge a écrit :
>> On 08/21/2012 05:14 AM, Andreas Färber wrote:
>>> So what about the non-MIPS32r2 case? IIUC then the SYNCI_Step register
>>> would no longer be accessible, which your commit message does not
>>> mention. Intentional?
>>
>> Yes, that is intentional.  In Section 9.13 of [1] it is stated that these
>> registers are only required starting at release 2 of the architecture.  The
>> Linux kernel follows the same approach.
> 
> Remember this is linux user mode, as such you should not look at the
> MIPS architecture, but rather at the behavour of MIPS architecture +
> Linux kernel. SYNCI_Step is emulated by the Linux kernel for non R2
> CPUs, as such it should be  available even for non R2 CPUs *in user mode
> only*. At a first glance, it seems to be the same for CPUNum, CC and
> CCRes, but someone has to check that more in details.

Ah, thanks Aurelien.  I see that in the kernel sources now.  Specifically,
it seems that 'simulate_rdhwr' handles the emulation [1] and that it includes
support for CPUNum, SYNCI_Step, CC, CCRes, and ULR (User Local register).  So,
I will remove the conditional.

I am not quite sure how to handle ULR at the moment.

[1]
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/mips/kernel/traps.c;h=9be3df1fa8a461dc4e1e5563582f483e4ed7c103;hb=HEAD

-- 
Meador Inge
CodeSourcery / Mentor Embedded
http://www.mentor.com/embedded-software