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[Qemu-devel] [PATCH v4 3/9] GICv3 support
From: |
Pavel Fedin |
Subject: |
[Qemu-devel] [PATCH v4 3/9] GICv3 support |
Date: |
Thu, 02 Jul 2015 17:14:01 +0300 |
From: Shlomo Pongratz <address@hidden>
Add system instructions used by the Linux (kernel) GICv3
device driver
Signed-off-by: Shlomo Pongratz <address@hidden>
---
target-arm/cpu.h | 12 ++++++
target-arm/cpu64.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 117 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 80297b3..c04b54c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1024,6 +1024,18 @@ void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);
+void armv8_gicv3_set_sgi(void *opaque, int cpuindex, uint64_t value);
+uint64_t armv8_gicv3_acknowledge_irq(void *opaque, int cpuindex,
+ MemTxAttrs attrs);
+void armv8_gicv3_complete_irq(void *opaque, int cpuindex, int irq,
+ MemTxAttrs attrs);
+uint64_t armv8_gicv3_get_priority_mask(void *opaque, int cpuindex);
+void armv8_gicv3_set_priority_mask(void *opaque, int cpuindex, uint32_t mask);
+uint64_t armv8_gicv3_get_sre(void *opaque);
+void armv8_gicv3_set_sre(void *opaque, uint64_t sre);
+uint64_t armv8_gicv3_get_igrpen1(void *opaque, int cpuindex);
+void armv8_gicv3_set_igrpen1(void *opaque, int cpuindex, uint64_t igrpen1);
+
/* Interface for defining coprocessor registers.
* Registers are defined in tables of arm_cp_reginfo structs
* which are passed to define_arm_cp_regs().
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 63c8b1c..7b0dee4 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -45,6 +45,72 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
#endif
+#ifndef CONFIG_USER_ONLY
+static void sgi_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ CPUState *cpu = ENV_GET_CPU(env);
+ armv8_gicv3_set_sgi(env->nvic, cpu->cpu_index, value);
+}
+
+static uint64_t iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ uint64_t value;
+ MemTxAttrs attrs;;
+ CPUState *cpu = ENV_GET_CPU(env);
+ attrs.secure = arm_is_secure_below_el3(env) ? 1 : 0;
+ value = armv8_gicv3_acknowledge_irq(env->nvic, cpu->cpu_index, attrs);
+ return value;
+}
+
+static void sre_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ armv8_gicv3_set_sre(env->nvic, value);
+}
+
+static uint64_t sre_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ uint64_t value;
+ value = armv8_gicv3_get_sre(env->nvic);
+ return value;
+}
+
+static void eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
+{
+ MemTxAttrs attrs;
+ CPUState *cpu = ENV_GET_CPU(env);
+ attrs.secure = arm_is_secure_below_el3(env) ? 1 : 0;
+ armv8_gicv3_complete_irq(env->nvic, cpu->cpu_index, value, attrs);
+}
+
+static uint64_t pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ uint64_t value;
+ CPUState *cpu = ENV_GET_CPU(env);
+ value = armv8_gicv3_get_priority_mask(env->nvic, cpu->cpu_index);
+ return value;
+}
+
+static void pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ CPUState *cpu = ENV_GET_CPU(env);
+ armv8_gicv3_set_priority_mask(env->nvic, cpu->cpu_index, value);
+}
+
+static uint64_t igrpen1_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ uint64_t value;
+ CPUState *cpu = ENV_GET_CPU(env);
+ value = armv8_gicv3_get_igrpen1(env->nvic, cpu->cpu_index);
+ return value;
+}
+
+static void igrpen1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
+{
+ CPUState *cpu = ENV_GET_CPU(env);
+ armv8_gicv3_set_igrpen1(env->nvic, cpu->cpu_index, value);
+}
+#endif
+
static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
@@ -89,6 +155,45 @@ static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
{ .name = "L2MERRSR",
.cp = 15, .opc1 = 3, .crm = 15,
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "EIOR1_EL1", .state = ARM_CP_STATE_AA64,
+#ifndef CONFIG_USER_ONLY
+ .writefn = eoir_write,
+#endif
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
+ { .name = "IAR1_EL1", .state = ARM_CP_STATE_AA64,
+#ifndef CONFIG_USER_ONLY
+ .readfn = iar_read,
+#endif
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0,
+ .access = PL1_R, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
+ { .name = "SGI1R_EL1", .state = ARM_CP_STATE_AA64,
+#ifndef CONFIG_USER_ONLY
+ .writefn = sgi_write,
+#endif
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5,
+ .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
+ { .name = "PMR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0,
+#ifndef CONFIG_USER_ONLY
+ .readfn = pmr_read, .writefn = pmr_write,
+#endif
+ .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
+ { .name = "CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
+ .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
+ { .name = "SRE_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, .resetvalue = 0,
+#ifndef CONFIG_USER_ONLY
+ .readfn = sre_read, .writefn = sre_write,
+#endif
+ .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
+ { .name = "IGRPEN1_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
+#ifndef CONFIG_USER_ONLY
+ .readfn = igrpen1_read, .writefn = igrpen1_write,
+#endif
+ .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 },
REGINFO_SENTINEL
};
--
1.9.5.msysgit.0
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, (continued)
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Daniel P. Berrange, 2015/07/02
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Pavel Fedin, 2015/07/02
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Christoffer Dall, 2015/07/02
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Pavel Fedin, 2015/07/02
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Christoffer Dall, 2015/07/02
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Pavel Fedin, 2015/07/03
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Christoffer Dall, 2015/07/03
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Pavel Fedin, 2015/07/03
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Christoffer Dall, 2015/07/03
- Re: [Qemu-devel] [PATCH v4 4/9] Add virt-v3 machine that uses GIC-500, Daniel P. Berrange, 2015/07/02
[Qemu-devel] [PATCH v4 3/9] GICv3 support,
Pavel Fedin <=
[Qemu-devel] [PATCH v4 7/9] Make use of kernel_irqchip_type in kvm_arch_irqchip_create(), Pavel Fedin, 2015/07/02
[Qemu-devel] [PATCH v4 1/9] Implement GIC-500 base class, Pavel Fedin, 2015/07/02
[Qemu-devel] [PATCH v4 2/9] Implement GIC-500, Pavel Fedin, 2015/07/02
Re: [Qemu-devel] [PATCH v4 0/9] GIC-500 implementation, software + KVM, Eric Auger, 2015/07/07