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[Qemu-devel] [PULL 03/14] target/mips: Weaken TLB flush on UX, SX, KX, A
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 03/14] target/mips: Weaken TLB flush on UX, SX, KX, ASID changes |
Date: |
Fri, 21 Jul 2017 03:37:04 +0100 |
From: James Hogan <address@hidden>
There is no need to invalidate any shadow TLB entries when the ASID
changes or when access to one of the 64-bit segments has been disabled,
since doing so doesn't reveal to software whether any TLB entries have
been evicted into the shadow half of the TLB.
Therefore weaken the tlb flushes in these cases to only flush the QEMU
TLB.
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Tested-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/helper.c | 2 +-
target/mips/op_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 166f0d1..11d6a86 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong
val)
#if defined(TARGET_MIPS64)
if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
/* Access to at least one of the 64-bit segments has been disabled */
- cpu_mips_tlb_flush(env);
+ tlb_flush(CPU(mips_env_get_cpu(env)));
}
#endif
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 6393eff..091afd5 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1416,7 +1416,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong
arg1)
/* If the ASID changes, flush qemu's TLB. */
if ((old & env->CP0_EntryHi_ASID_mask) !=
(val & env->CP0_EntryHi_ASID_mask)) {
- cpu_mips_tlb_flush(env);
+ tlb_flush(CPU(mips_env_get_cpu(env)));
}
}
--
2.7.4
- [Qemu-devel] [PULL 00/14] target-mips queue, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 01/14] target/mips: Fix MIPS64 MFC0 UserLocal on BE host, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 03/14] target/mips: Weaken TLB flush on UX, SX, KX, ASID changes,
Yongbok Kim <=
- [Qemu-devel] [PULL 02/14] target/mips: Fix TLBWI shadow flush for EHINV, XI, RI, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 04/14] target/mips: Add CP0_Ebase.WG (write gate) support, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 07/14] target/mips: Decode microMIPS EVA load & store instructions, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 08/14] target/mips: Check memory permissions with mem_idx, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 06/14] target/mips: Decode MIPS32 EVA load & store instructions, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 13/14] target/mips: Add EVA support to P5600, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 10/14] target/mips: Add an MMU mode for ERL, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 09/14] target/mips: Abstract mmu_idx from hflags, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 05/14] target/mips: Prepare loads/stores for EVA, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 12/14] target/mips: Implement segmentation control, Yongbok Kim, 2017/07/20