[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqM
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA |
Date: |
Fri, 25 May 2018 14:51:04 +0100 |
On 18 May 2018 at 18:19, Peter Maydell <address@hidden> wrote:
> From: Francisco Iglesias <address@hidden>
>
> Add a model of the generic DMA found on Xilinx ZynqMP.
Hi; the latest Coverity run finds a couple of issues in this code:
> +static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + XlnxZDMA *s = XLNX_ZDMA(opaque);
> + RegisterInfo *r = &s->regs_info[addr / 4];
> +
> + if (!r->data) {
> + qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
> + object_get_canonical_path(OBJECT(s)),
> + addr);
object_get_canonical_path() returns a string that the caller
takes ownership of, so you have to g_free() it when you've
finished with it. (CID 1391294)
> + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
> + zdma_ch_imr_update_irq(s);
> + return 0;
> + }
> + return register_read(r, ~0, NULL, false);
> +}
> +
> +static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + XlnxZDMA *s = XLNX_ZDMA(opaque);
> + RegisterInfo *r = &s->regs_info[addr / 4];
> +
> + if (!r->data) {
> + qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
> + object_get_canonical_path(OBJECT(s)),
> + addr, value);
Similarly here. (CID 1391293)
> + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
> + zdma_ch_imr_update_irq(s);
> + return;
> + }
> + register_write(r, value, ~0, NULL, false);
> +}
Could you write a patch that adds the missing g_free()s, please?
thanks
-- PMM
- [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 03/32] target/arm: Add the XML dynamic generation, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 02/32] target/arm: Add "_S" suffix to the secure version of a sysreg, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 05/32] xlnx-zynqmp: Connect the ZynqMP GDMA and ADMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 09/32] target/arm: Add SVE decode skeleton, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 08/32] target/arm: Introduce translate-a64.h, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 11/32] target/arm: Implement SVE load vector/predicate, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 19/32] target/arm: Implement SVE bitwise shift by wide elements (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 12/32] target/arm: Implement SVE predicate test, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 13/32] target/arm: Implement SVE Predicate Logical Operations Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Unpredicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 18/32] target/arm: Implement SVE bitwise shift by vector (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Group, Peter Maydell, 2018/05/18