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Re: [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus |
Date: |
Fri, 17 Aug 2018 20:08:42 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
Hi Alistair,
On 08/16/2018 01:11 PM, Alistair Francis wrote:
> To allow Linux to ennumerate devices on the /soc/ node set it as a
enumerate
> "simple-bus".
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 248bbdffd3..e8ba4d192d 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -121,7 +121,7 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
>
> qemu_fdt_add_subnode(fdt, "/soc");
> qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
> - qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
> + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
For consistency can you do the same patch for the Spike board?
> qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
> qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
- [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/08/16
- Re: [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/08/16