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Re: [Simulavr-devel] need help to fix some issues in build toolchain


From: Klaus Rudolph
Subject: Re: [Simulavr-devel] need help to fix some issues in build toolchain
Date: Mon, 2 Nov 2015 09:45:04 +0100

Hi Thomas,
> 
> You wrote, that this works on verilog v10 or higher. I had a look in my 
> box and this showed for iverilog command version 0.9.7. (ubuntu 14.04)

I had a discussion on http://electronics.stackexchange.com/ which ends up in 
"It is a bug with Icarus 0.9.6 & 0.9.7 on edaplayground." Edaplayground serves 
a online setup for a lot of free verilog compilers. As mentioned all versions 
before v10
are not able to handle the "strength" by driving one wire from multiple sources 
correctly.

As a result I decided to recommend v10 and nothing earlier.


> 
> So the first question is: what's the output of "iverilog -V | head -1" 
> (what's the version string) (same for vpp command, but this should 
> normaly be the same)

Attention for the piping of output of vvp version information! The 
output is written on stderr not stdout!

$> /opt/verilog/v10/bin/vvp -V 2>&1 >/dev/null |head -1
Icarus Verilog runtime version 10.0 (stable) (v10_0)

$> /opt/verilog/v10/bin/iverilog -V
Icarus Verilog version 10.0 (stable) (v10_0)
Unable to get version from "/opt/verilog/v10/lib/ivl/ivlpp -V"
Unable to get version from "/opt/verilog/v10/lib/ivl/ivl -V 
-C"/tmp/ivrlh2dd33e0a" -C"/opt/verilog/v10/lib/ivl/vvp.conf""

First line was written on stdout, rest is stderr.

> 
> What's your distribution?
Fedora 22, The version delivered with the package managers is still 0.9.6 what 
is very bad!

> You wrote, that you installed the newer 
> version in an other place. Is this just for testing purpose? Background 
> for this is, how to detect the right installation with header and libs.

No, this is for "production" :-) I started using verilog a week ago. I have 
nearly none experience with the
tool and the installation process and results. But I trust in the installation 
script :-)

For a test of functionality it should be possible to write a small verilog 
"program" and run the compiler
and runtime engine and check if the result is written to an output file. It is 
also possible
to manually write something to stdout which can be checked. If it helps I can 
provide
a short prog which will write something to stdout if the tool works. If can't 
guarantee that
everything ( e.g. libraries ) are in place if the test completes...

> Maybe I have to implement the possibility to assign a special path for 
> detection in configure script.

That would be very great! As I see there are already some variables for VERILOG 
and VVP.
If they are set correctly I hope that everything is fine.

I will send you the simple verilog prog which produces some output to check if 
the version
works as expected. Maybe I can check for the broken assignment to get also a 
version check there.

Regards,
 Klaus




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