Re: [Simulavr-devel] need help to fix some issues in build toolchain

[Klaus Rudolph]

Hi Thomas,

as mentioned in my first mail from today here is the example code
to verify the call to verilog ( iverilog & vvp ).
It can also be used if the pull up bug is present or not.
The verilog code is:

// file test.v
module check;

wire result;
reg in_drive = 1'bz;
reg drive_enable = 1'b0;
reg pull_enable = 1'b0;

assign ( pull0, pull1) result = pull_enable ? 1'b1 : 1'bz;
assign                 result = drive_enable ? in_drive : 1'bz;

initial begin
    pull_enable = 1'b1;
    in_drive = 1'b0;
    drive_enable = 1'b1;
    #1 $display("Value:%b %v", result, result);
    $finish;
end

endmodule


###########
And a Makefile, which can be used to check 2 versions of iverilog installation.

// file: Makefile
all: test.vcd

# run with v10
#VVP=/opt/verilog/v10/bin/vvp
#IVERILOG=/opt/verilog/v10/bin/iverilog

# run with older ( buggy ) version
IVERILOG = /usr/bin/iverilog
VVP = /usr/bin/vvp

%.vvp: %.v 
    $(IVERILOG) $< -o $@

%.vcd: %.vvp
    $(VVP) $<

clean:
    rm -f *.vcd
    rm -f *.vvp

###

If you run the example code, the output will be:

1) Good ( v10 ) output:
Value:0 St0

2) Bad ( v 0.9.6 or 0.9.7 )
Value:x StX

If the check works and the result is as expected I also expect that the 
installation of
verilog is ok.

If you need additional information feel free to ask!

Thanks
 Klaus