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Re: [avr-gcc-list] r-engineering the JTAG-ICE protocol
From: |
Karl Ran |
Subject: |
Re: [avr-gcc-list] r-engineering the JTAG-ICE protocol |
Date: |
Sat, 05 Oct 2002 15:56:39 +0000 |
Hi Jesper,
I've been thinking of the same thing. Haven't started yet, but are
considering buying a JTAGICE so I can hack it.
Yep: buy it, r-engineer it, dump it.....:(
The protocols is as you say synchronous, so a simple program
could be written on a mega16x or 8515 to log all the communication
between the ICE and the CPU being debugged.
There are 4 signals for the TAP controller:
TMS its a 3 bit mode selector :-/
TCK clock
TDI data in
TDO data out
Or, if it's too fast, the good old way with a storage scope works
too.
JTAG port bitrate can be 50, 100, 200 kHz.
We could use software polling or maybe a SPI port(s)...
A first step probably would be to write a little prog. to dump the JTAG
traffic to a host computer via RS232...
Karl
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