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Re: [avr-gcc-list] jtagice and stk500 protocol docs

From: Karl Ran
Subject: Re: [avr-gcc-list] jtagice and stk500 protocol docs
Date: Mon, 07 Oct 2002 19:24:51 +0000

The proprietary stuff is the jtag debugging protocol implemented within
the silicon of the AVR devices. This is what you guys propose to reverse
engineer and is the interface from the jtagice to the device.

The good thing is that the low layer of the protocol is compatible with ieee1149.1(aka JTAG).
We have to find out what the 4 commands do:


The Mega128 pdf says:
All read or modify/write operations needed for implementing the
Debugger are done by applying AVR instructions via the internal AVR
CPU Scan Chain. The CPU sends the result to an I/O memory mapped
location which is part of the communication interface between the
CPU and the JTAG system.

So, it shouldn't be that difficult...

If you guys can successfully rev-eng the lower level interface, there may
still need to be a piece of hardware sitting between gdb and the device
which could be similar to the atmel jtagice box, but completely open and
compatible, possibly even using the same avrstudio <-> jtagice protocol.

Well, if we want to push gdb, we have to make it incompatible ;-)

who is not sure which mailing list would be OK for these topics :-/

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