Re: [avr-gcc-list] jtagice and stk500 protocol docs

[a . doesschate]

On Mon, Oct 07, 2002 at 10:22:37PM +0000, Karl Ran wrote:
> >The JTAG clock is slow as from  Atmel's JTAGICE box, a few hundered > kHz 
> >at most from memory.
> 
> OK, it's time now for some action!
> 
> Would anyone w/ a JTAGICE box please hook the TCLK signal up to his scope 
> and send us the period-time of the JTAG clock?
> 

<snip>

Here are my results :
On chip debug           state change (T)        DR/IR state (T)
communication freq.
according to Atmel

125 KHz                 8.5                     10 - 12
250 KHz                 5.4                     7.1 - 9
500 KHz                 3.9                     5.5 - 7
1000 KHz                2.4                     4 - 5.8

Remarks :
- all figures are periods (in microseconds)
- state change means that the TAP controller is going from one 
  state to the next state without doing anything with the TDI/TDO
  levels. 
- DR/IR state means that data will be clocked in and out of the 
  data/instruction registers in this state and depends how many
  bytes will be up/downloaded. 
- The ATmega163 inside the JTAG ICE must keep track of the data to
  be clocked in and out when in DR/IR state. The levels of TDI and
  TDO must be checked so it will take more time in this phase.
- Above mentioned means that during a JTAG message the TCK will
  not be constant. 
- There are some very small variations in these measurements but
  they should be under 0.2 microseconds.

 All measurements are done with a Tektronix TDS 220.

Hope this helps ...


Armand


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Armand ten Doesschate
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