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Re: [avr-gcc-list] optimizing multiplies with mixed sizes

From: E. Weddington
Subject: Re: [avr-gcc-list] optimizing multiplies with mixed sizes
Date: Fri, 27 Aug 2004 13:58:34 -0600
User-agent: Mozilla Thunderbird 0.7.3 (Windows/20040803)

address@hidden wrote:

Has any work been done on optimizing multiplies involving mixed sizes?
It seems that gcc could do a better job.  The extra clr, mul, and add
are kind of painful to see.

The problem, I guess, is that the intermediate values are all 16-bit
(since that's the size of an int on the AVR) and presumably are
represented as 16-bit values in the RTL, where most of the
optimization takes place, but the RTL optimizer doesn't know about the
mapping of RTL registers to pairs of 8-bit registers, so we don't get
the obvious optimizations happening.

Is there any scope for adding some sort of optimization stage after the
conversion to 8-bit register code that will get rid of some of this stuff
(my knowledge of GCC internals is limited to a quick eyeballing of the
relevant parts of the code)?

Seems that in all these cases it would be nice to have something like
another RTL optimizer working on operations with bytes (see the cited
thread for suboptimal assembly generated by gcc for these examples).

I know very little of gcc internals, so I just guess now: Adding
another RTL optimizer at that place is probably very hard, but maybe
it would be possible to do it all in one RTL optimizer if conversion
to 8-bit operations were somehow done as a transformation in RTL?
(Waiting for comments shouting out how childish my idea is...)

I just wanted to point out that GCC internals have changed dramatically between the 3.4 series and what is currently in HEAD (the upcoming 3.5 series). I don't know for sure if adding an RTL opitimizer is a good idea. The optimizer would have to be in another format/place.


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