[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [avr-gcc-list] interrupts and signals (again)

From: Parthasaradhi Nayani
Subject: Re: [avr-gcc-list] interrupts and signals (again)
Date: Sat, 26 Mar 2005 09:20:54 -0800 (PST)

--- David Kelly <address@hidden> wrote:
> On more advanced CPU's interrupts behave as Jamie
> was asking. That only 
> a higher priority interrupt can suspend a lower
> priority handler in 
> execution.
> On microcontrollers where low cost and high volume
> is the name of the 
> game it was once common to have only one interrupt
> vector, or none. Off 
> the top of my head a Microchip 16C55x has one IRQ
> which shares the same 
> vector as power up. One has to determine which event
> happened in 
> software.
> AVRs are pretty advanced with lots of IRQ vectors,
> most are self 
> clearing.

IMHO all processors/controllers disable the global
interrupt once the ISR is entered except for NMIs,
which can never be disabled. I am not sure of any 
advanced processors which selectively enable higher
priority interrupts when a lower priority interrupt is
being serviced. Can you give some example (chip
numbers) processors/controllers.


Do you Yahoo!? 
Yahoo! Small Business - Try our new resources site!

reply via email to

[Prev in Thread] Current Thread [Next in Thread]