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RE: [avr-gcc-list] interrupts and signals (again)

From: Jamie Morken
Subject: RE: [avr-gcc-list] interrupts and signals (again)
Date: Sat, 26 Mar 2005 13:45:36 -0800


Thanks all for the help, I was confused because I am using the PWM to drive a 
motor and the PWM signal looked fine (on my ancient oscilloscope anyway!) but 
the motor was faltering once or twice a second, so I thought it was an 
intermittent ISR bug, but the problem was with the bridge driver IC (ir21844 
from IRF.com) it has two control lines, a disable and a pin to select the 
highside or lowside fet, and my code changed those two signals simultaneously, 
and when I switched to changing them seperately the motor problem disappeared - 
hard to track down bug! :)

original line:
PORTD = (PORTD & ~(_BV(h3in))) | (_BV(h2in) | _BV(h2dis) | _BV(h3dis));

new lines:
PORTD = (PORTD & ~(_BV(h3in))) | (_BV(h2dis) | _BV(h3dis));
PORTD |= BV(h2in);


----- Original Message -----
From: Larry Barello <address@hidden>
Date: Saturday, March 26, 2005 10:25 am
Subject: RE: [avr-gcc-list] interrupts and signals (again)

> The intel x86 interrupt controller family comes to mind.  This is 
> ancienthistory, but the i8259 comes to mind.  I think all that 
> stuff is embedded in
> the CPU chips now days.
> If you think of interrupts as the hardware equivalent to tasks in 
> an OS,
> then priority and pre-emption makes sense.  The AVR has priority 
> (the order
> of the vector table) but not priority based pre-emption.
> -----Original Message-----
> From: Parthasaradhi Nayani
> Hello,
> IMHO all processors/controllers disable the global
> interrupt once the ISR is entered except for NMIs,
> which can never be disabled. I am not sure of any
> advanced processors which selectively enable higher
> priority interrupts when a lower priority interrupt is
> being serviced. Can you give some example (chip
> numbers) processors/controllers.
> Nayani
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> AVR-GCC-list mailing list
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