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RE: [avr-gcc-list] interrupts and signals (again)

From: Larry Barello
Subject: RE: [avr-gcc-list] interrupts and signals (again)
Date: Sat, 26 Mar 2005 10:25:07 -0800

The intel x86 interrupt controller family comes to mind.  This is ancient
history, but the i8259 comes to mind.  I think all that stuff is embedded in
the CPU chips now days.

If you think of interrupts as the hardware equivalent to tasks in an OS,
then priority and pre-emption makes sense.  The AVR has priority (the order
of the vector table) but not priority based pre-emption.

-----Original Message-----
From: Parthasaradhi Nayani

IMHO all processors/controllers disable the global
interrupt once the ISR is entered except for NMIs,
which can never be disabled. I am not sure of any
advanced processors which selectively enable higher
priority interrupts when a lower priority interrupt is
being serviced. Can you give some example (chip
numbers) processors/controllers.


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