Re: [avr-gcc-list] how to infer lsl instruction...

[Terry Karlson]

Lars Noschinski wrote:

> Look at the Atmel AVR instruction set datasheet, and you will see, that
> "lsl r" and "rol r" have the same opcodes as "add r,r" and "adc r,r".

The document this thread is referring to is most likely
http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf.

For those who haven't encountered all of these yet, the complete list is:

SBR -> ORI
CBR -> ANDI
TST -> AND
CLR -> EOR
LSL -> ADD
ROL -> ADC
all branch instructions -> BRBS, BRBC

For example, in the above document, in the particular entry for CLR,
with "16-bit Opcode" it says "see EOR Rd,Rd" (which one has certainly
seen if they've looked at disassembly).  (It would have been nice if all
these equivalencies were more than just hinted at in the table summary.)

Even BRGE and BRLT, which formally depend on both the N and V bits, are
done with BRBS and BRBC via the S bit.  On the other hand, this is why
there is no "BRGT" (branch if greater than zero, signed) nor "BRLE"
(branch if less than or equal, signed).

-Terry Karlson