[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Discuss-gnuradio] grGPS Preliminary Schematic

From: Robert W McGwier
Subject: Re: [Discuss-gnuradio] grGPS Preliminary Schematic
Date: Thu, 06 Apr 2006 10:39:40 -0400
User-agent: Mozilla Thunderbird 1.0.6 (X11/20050715)

David Bengtson wrote:
Martin Dvh wrote:
Why don't you use the usrp to generate your 16.384 or 32.768 MHz refclock. Most daugterboards (except the tvrx) use this feature (They all use a 4Mhz refclock on io pin 0.
The only difference with your design is that you need another frequency.
The cyclone fpga in the usrp has internal PLLs which can generate all kinds of frequencies.
(They are not used at the moment)

(Sorry, there is a typo, the reference frequencies are 16.368/32.736 MHz)
That might work. 16.368 MHz/4 MHz is 1023/250, or a comparison frequency of 16 kHz. From a frequency generation point of view, I could probably get the right frequency from the USRP I'm concerned about jitter and noise on that line though. The reference is used directly for the comparison frequency in the on-chip PLL, to generate a LO that is 1571.328 MHz. A 16 kHz
The generation of 1571.328 from this source is almost surely a deal killer because of the phase noise. That LO must be accurate, stable, and as phase noise free as possible. We are trying to work with a signal of only a few dB dynamic range signal and it is weak, right at the noise floor in most systems. Cascaded LNA's will bring the signal up but also lower the IP3 and the dynamic range and greatly increase the front end susceptibility to overload, interference, and collapse. This particular oscillator and the attendant mixer cannot be scrimped on. At least do a serious noise budget analysis to make sure the system will actually be usable after built.

spurious on this would really cause problems.

Because of this, I'd like to use a a clean reference clock for the reference. I could change the layout to bring a signal over from the connector to the reference input to check that though. That would make it possible to try this approach.

Re-Using the reference clock is why I brought the buffered clock signal over to the connector, so that it will be available to the FPGA.


Robert W. McGwier, Ph.D.
Center for Communications Research
805 Bunn Drive
Princeton, NJ 08540

reply via email to

[Prev in Thread] Current Thread [Next in Thread]