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[Discuss-gnuradio] tx_chain - Verilog question


From: Ronald Jetli
Subject: [Discuss-gnuradio] tx_chain - Verilog question
Date: Fri, 30 Nov 2007 01:40:36 -0500

Hi,

My questions is regarding tx_chain.v.
 
I am a bit confused as to how the flow of the code would proceed. There is no "always" statement in the code.

First, two instances of cic_interp are instantiated .i.e.  cic_interp_i & cic_interp_q . The signal assignments happen. The most significant signals i_in and q_in are assigned to signal_in of cic_interp_i & cic_interp_q.

Question 1:

Do both (cic_interp_i & cic_interp_q) instantiation and assignment happen at the execution time 0 ?

Or for that matter, all (cic_interp_i ,  cic_interp_q, phase_acc_tx & tx_cordic_0) instantiations happen at time 0 ?

I am doubtful of what I am thinking above. Because I can see that cic_interp_i's output signal bb_i is being assigned as input in tx_cordic_0. So, if I go by my logic, then wrong assignments would happen.

Question 2:

Lets assume that some logic is defined for all (cic_interp_i ,  cic_interp_q, phase_acc_tx & tx_cordic_0) modules. And suppose cic_inter_i module logic takes 5 clock cycles to finish its task and tx_cordic_0 module logic takes 8 clock cycles to finish its task. So, will tx_cordic_0 wait for 5 clock cycles for cic_interp_i to finish its task, produce bb_i and then tx_cordic_0 uses this new bb_i and then takes additional 8 clock cycles to finish its task ?
So, total completion time would be 13 clock cycles ? Am I thinking right or there is something wrong ?

Thanks !

Jetli.

P.S. Excuse me if my understanding sounds naive.

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