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Re: [Discuss-gnuradio] Re: tx_chain - Verilog question


From: Ronald Jetli
Subject: Re: [Discuss-gnuradio] Re: tx_chain - Verilog question
Date: Fri, 30 Nov 2007 18:29:56 -0500

Thank you Brian !

I am posting the test bench I am using to simulate / test tx_chain buffer.  I think it has
been set up properly to simulate CIC. And I do follow the steps while stimulating.

However, I am having trouble setting up test cases for phase accumulator / Cordic.

I am posting the code below. It should'nt take much change (atmost few lines), but I am stuck with this one.It just dosent seem to work
for Cordic / Phase accumulator.

Can anyone please chip in ?

The Cordic test bench in fpga folder wasen't good either. It needs "sine.txt" file, which is missing.

Thanks.

Jetli.

Testbench:
---------------


module tb;

  // Things that will be inputs to the device under test
  // (DUT) are declared as "reg" so I can write to them
  reg clock;
  reg reset;
  reg enable;
  reg sample_strobe;
  reg interpolator_strobe;
  reg [7:0] interp_rate ;
  reg [31:0] freq ;
  reg [15:0] i_in ;
  reg [15:0] q_in ;
  //int seed ;
 
  // Things that will be outputs from the DUT are wires.
  // Observe them with the simulator's waveform viewer.
  wire [15:0] i_out ;
  wire [15:0] q_out ;

  // The device under test
   tx_chain testing (clock,reset,enable,interp_rate,sample_strobe,interpolator_strobe,freq,i_in,q_in,i_out, q_out);
   


  reg stop;  // needed to stop simulation running for ever

  // Reset generator
  initial begin
    // Assert reset
    reset = 1'b1;
    // Wait for two clock cycles...
    repeat (2) @(negedge clock);
    // then deassert reset
    reset = 1'b0;
  end

  // clock generator
  initial begin
    stop = 1'b0;
    clock = 1'b0;
    while (!stop)
      #5 clock = ~clock;
  end

  // stimulus generator
  initial begin : stim_gen

   integer seed;

    // Set up seed for random stimulus generator
    seed = 42;
   
// Set up sensible values on control inputs
   
    interp_rate = 3;
    freq = 20;
   
    // Jamming input to true to see what happens.
    enable = 1'b1;

    // Now generating some input over the first 100 clocks
    repeat (100) @(negedge clock) begin
      // Randomly asserting strobe signals with 50% probability
      sample_strobe = $dist_uniform(seed, 0, 1);
      interpolator_strobe = $dist_uniform(seed, 0, 1);
      // Random 16-bit values on quadrature inputs
      i_in = $dist_uniform(seed, -32768, 32767);
      q_in = $dist_uniform(seed, -32768, 32767);
     // bb_i = $dist_uniform(seed, -32768, 32767);
    //  bb_q = $dist_uniform(seed, -32768, 32767);
    end

    // And finally stop:
    stop = 1;

  end

endmodule
   

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