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Re: [Help-gnucap] gnucap error

From: Ramiro Aceves
Subject: Re: [Help-gnucap] gnucap error
Date: Thu, 07 Jul 2011 11:54:38 +0200
User-agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv: Gecko/20110505 Iceowl/1.0b1 Icedove/3.0.11

Thanks Al for your response. It is a pleasure to have feedback from the autor of GNUCAP. Congrats!

Oh, I am using gnucap 0.35 from Debian Stable. I will install latest snapshot and see. I watched the page and saw that 0.35 was the stable release and thought that no improvements were made since that.

latest one seems to be from 2009-12-07. is it the right one?

Thank you very much and congrats for this great software



El 07/07/11 04:49, al davis escribió:
On Wednesday 06 July 2011, Andy Fierman wrote:
I'm not experienced with Gnucap so please excuse me if this
is nonsense.

Is the

DVnoise.X1, Dvnoise is not a .model

part of the error message is trying to tell you that the line

***Voltage Noise Generation

DVnoise 501     0       Dvnoise

is confusing the parsing process (not sure if that's the
right terminology but I hope you get the idea)?

Maybe the net name "DVnoise" at the start of the line is
being read as the diode component "Dvnoise". This could
cause a problem.

Yes .. that's it.

Model names and device names are in the same scope.

That raises a question ...  How is this handled in the various
versions of Spice?  I thought it was the same, but I keep
finding surprises in the many variants of spice format.  I
consider "HSpice" to be the most important for compatibility,
and "PSpice" second.  Both of these are Spice-2 derivatives.

That's one of the reasons to move away from spice format
netlists.  In recent snapshots, the language is a plugin.
Verilog and Spectre formats are also supported, and much

If Gnucap is case sensitive when reading netlists then a
component called DVnoise would not be the same as Dvnoise
and so the .model Dvnoise would not be seen as applying to
the wrongly identified DVnoise component.

In recent snapshots, there is an option to make it case
sensitive or not.  By default, it is case sensitive with Verilog
or Spectre formats, insensitive with Spice format ... for
compatibility with the published or accepted spec of each

You should get the latest snapshot from  There are a
lot of improvements since 0.35.


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