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Loops in makefile

From: dsudha
Subject: Loops in makefile
Date: Thu, 10 Jul 2003 08:46:10 -0600

Hello all I have a variable from which my target names are derived, for example listvar = a b c p l w q x y The targets are made as follows
apnd.t : apnd.s a.h
bpnd.t : bpnd.s b.h
xpnd.t : xpnd.s x.h
ypnd.t : ypnd.s y.h

Is there any way I can loop through $(listvar) in the makefile instead of explicitly writing them all out?

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