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[PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 to bool
From: |
Richard Henderson |
Subject: |
[PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 to bool |
Date: |
Sun, 17 Apr 2022 10:43:32 -0700 |
Bool is a more appropriate type for this value.
Adjust the assignments to use true/false.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 +-
target/arm/cpu.c | 2 +-
target/arm/helper-a64.c | 4 ++--
target/arm/helper.c | 2 +-
target/arm/hvf/hvf.c | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9ae9c935a2..a61a52e2f6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -258,7 +258,7 @@ typedef struct CPUArchState {
* all other bits are stored in their correct places in env->pstate
*/
uint32_t pstate;
- uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
+ bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
/* Cached TBFLAGS state. See below for which bits are included. */
CPUARMTBFlags hflags;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5d4ca7a227..30e0d16ad4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -189,7 +189,7 @@ static void arm_cpu_reset(DeviceState *dev)
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
/* 64 bit CPUs always start in 64 bit mode */
- env->aarch64 = 1;
+ env->aarch64 = true;
#if defined(CONFIG_USER_ONLY)
env->pstate = PSTATE_MODE_EL0t;
/* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 7cf953b1e6..77a8502b6b 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -952,7 +952,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
qemu_mutex_unlock_iothread();
if (!return_to_aa64) {
- env->aarch64 = 0;
+ env->aarch64 = false;
/* We do a raw CPSR write because aarch64_sync_64_to_32()
* will sort the register banks out for us, and we've already
* caught all the bad-mode cases in el_from_spsr().
@@ -975,7 +975,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
} else {
int tbii;
- env->aarch64 = 1;
+ env->aarch64 = true;
spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
pstate_write(env, spsr);
if (!arm_singlestep_active(env)) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7d14650615..47fe790854 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10182,7 +10182,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
}
pstate_write(env, PSTATE_DAIF | new_mode);
- env->aarch64 = 1;
+ env->aarch64 = true;
aarch64_restore_sp(env, new_el);
helper_rebuild_hflags_a64(env, new_el);
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 8c34f86792..11176ef252 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -565,7 +565,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)
hv_return_t ret;
int i;
- env->aarch64 = 1;
+ env->aarch64 = true;
asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz));
/* Allocate enough space for our sysreg sync */
--
2.25.1
- [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus, Richard Henderson, 2022/04/17
- [PATCH v3 02/60] target/arm: Update ISAR fields for ARMv8.8, Richard Henderson, 2022/04/17
- [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8, Richard Henderson, 2022/04/17
- [PATCH v3 01/60] tcg: Add tcg_constant_ptr, Richard Henderson, 2022/04/17
- [PATCH v3 04/60] target/arm: Update SCTLR bits to ARMv9.2, Richard Henderson, 2022/04/17
- [PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 to bool,
Richard Henderson <=
- Re:, Alex Bennée, 2022/04/19
- [PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool, Richard Henderson, 2022/04/17
- [PATCH v3 18/60] target/arm: Use tcg_constant in translate-m-nocp.c, Richard Henderson, 2022/04/17
- [PATCH v3 08/60] target/arm: Change DisasContext.thumb to bool, Richard Henderson, 2022/04/17