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[PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool
From: |
Richard Henderson |
Subject: |
[PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool |
Date: |
Sun, 17 Apr 2022 10:43:31 -0700 |
Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 2 +-
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 3a0db801d3..8b7dd1a4c0 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -59,12 +59,12 @@ typedef struct DisasContext {
* so that top level loop can generate correct syndrome information.
*/
uint32_t svc_imm;
- int aarch64;
int current_el;
/* Debug target exception level for single-step exceptions */
int debug_target_el;
GHashTable *cp_regs;
uint64_t features; /* CPU features bits */
+ bool aarch64;
/* Because unallocated encodings generate different exception syndrome
* information from traps due to FP being disabled, we can't do a single
* "is fp access disabled" check at a high level in the decode tree.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9333d7be41..4dad23db48 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14664,7 +14664,7 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->isar = &arm_cpu->isar;
dc->condjmp = 0;
- dc->aarch64 = 1;
+ dc->aarch64 = true;
/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
* there is no secure EL1, so we route exceptions to EL3.
*/
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bf2196b9e2..480e58f49e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9334,7 +9334,7 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
dc->isar = &cpu->isar;
dc->condjmp = 0;
- dc->aarch64 = 0;
+ dc->aarch64 = false;
/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
* there is no secure EL1, so we route exceptions to EL3.
*/
--
2.25.1
- Re: [PATCH v3 02/60] target/arm: Update ISAR fields for ARMv8.8, (continued)
- [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8, Richard Henderson, 2022/04/17
- [PATCH v3 01/60] tcg: Add tcg_constant_ptr, Richard Henderson, 2022/04/17
- [PATCH v3 04/60] target/arm: Update SCTLR bits to ARMv9.2, Richard Henderson, 2022/04/17
- [PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 to bool, Richard Henderson, 2022/04/17
- Re:, Alex Bennée, 2022/04/19
- [PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool,
Richard Henderson <=
- [PATCH v3 18/60] target/arm: Use tcg_constant in translate-m-nocp.c, Richard Henderson, 2022/04/17
- [PATCH v3 08/60] target/arm: Change DisasContext.thumb to bool, Richard Henderson, 2022/04/17
- [PATCH v3 09/60] target/arm: Change CPUArchState.thumb to bool, Richard Henderson, 2022/04/17