[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] Bug report about x86 'bt' insn
From: |
malc |
Subject: |
Re: [Qemu-devel] Bug report about x86 'bt' insn |
Date: |
Wed, 10 Nov 2010 18:45:37 +0300 (MSK) |
User-agent: |
Alpine 2.00 (LNX 1167 2008-08-23) |
On Wed, 10 Nov 2010, malc wrote:
> On Wed, 10 Nov 2010, Torbjorn Granlund wrote:
>
> > malc <address@hidden> writes:
> >
> > All is the keyword here, i doubt that exhaustive search was performed
> > furthermore, AMDs documentation (to the best of my knowledge still)
> > still maintains that ZF is undefined.
> >
> > AMD indeed still says undefined in their documentation (as of two hours
> > ago). I have asked AMD for a clarification, mainly to make sure they
> > are aware of Intel's documentation change.
> >
> > (I am not certain about what you doubt. As I said, I did not check all
> > 2^64 operand values combined all possible bt bit position arguments. I
> > believe I have checked all 64-bit x86 processors implementations [two
> > generations of Core2, NHM and WSM based Core ix, Via Nano, as well as all
> > Athlon64/Opteron generations).)
>
> I meant all CPU variants.
Anyways:
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7b6e3c2..f416dce 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -6536,8 +6536,7 @@ static target_ulong disas_insn(DisasContext *s,
target_ulong pc_start)
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
switch(op) {
case 0:
- tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
- tcg_gen_movi_tl(cpu_cc_dst, 0);
+ tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
break;
case 1:
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
@@ -6560,7 +6559,14 @@ static target_ulong disas_insn(DisasContext *s,
target_ulong pc_start)
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
break;
}
- s->cc_op = CC_OP_SARB + ot;
+
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_compute_eflags(cpu_cc_src);
+ tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, CC_C);
+ tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp4);
+ s->cc_op = CC_OP_EFLAGS;
+
if (op != 0) {
if (mod != 3)
gen_op_st_T0_A0(ot + s->mem_index);
--
mailto:address@hidden
- Re: [Qemu-devel] Bug report about x86 'bt' insn, (continued)
- Re: [Qemu-devel] Bug report about x86 'bt' insn, malc, 2010/11/06
- Re: [Qemu-devel] Bug report about x86 'bt' insn, Torbjorn Granlund, 2010/11/06
- Re: [Qemu-devel] Bug report about x86 'bt' insn, malc, 2010/11/06
- Re: [Qemu-devel] Bug report about x86 'bt' insn, Nathan Froyd, 2010/11/06
- Re: [Qemu-devel] Bug report about x86 'bt' insn, malc, 2010/11/06
- Re: [Qemu-devel] Bug report about x86 'bt' insn, malc, 2010/11/06
- Re: [Qemu-devel] Bug report about x86 'bt' insn, Torbjorn Granlund, 2010/11/10
- Re: [Qemu-devel] Bug report about x86 'bt' insn, malc, 2010/11/10
- Re: [Qemu-devel] Bug report about x86 'bt' insn, Torbjorn Granlund, 2010/11/10
- Re: [Qemu-devel] Bug report about x86 'bt' insn, malc, 2010/11/10
- Re: [Qemu-devel] Bug report about x86 'bt' insn,
malc <=