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[Qemu-devel] [PATCH 10/10] target-i386: SSE4.2: use clz32/ctz32 instead
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 10/10] target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel |
Date: |
Tue, 26 Mar 2013 20:01:42 +0100 |
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-i386/fpu_helper.c | 1 +
target-i386/ops_sse.h | 32 ++------------------------------
2 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c
index 44f3d27..29a8fb6 100644
--- a/target-i386/fpu_helper.c
+++ b/target-i386/fpu_helper.c
@@ -20,6 +20,7 @@
#include <math.h>
#include "cpu.h"
#include "helper.h"
+#include "qemu/host-utils.h"
#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h
index a0bac07..a11dba1 100644
--- a/target-i386/ops_sse.h
+++ b/target-i386/ops_sse.h
@@ -2064,34 +2064,6 @@ static inline unsigned pcmpxstrx(CPUX86State *env, Reg
*d, Reg *s,
return res;
}
-static inline int rffs1(unsigned int val)
-{
- int ret = 1, hi;
-
- for (hi = sizeof(val) * 4; hi; hi /= 2) {
- if (val >> hi) {
- val >>= hi;
- ret += hi;
- }
- }
-
- return ret;
-}
-
-static inline int ffs1(unsigned int val)
-{
- int ret = 1, hi;
-
- for (hi = sizeof(val) * 4; hi; hi /= 2) {
- if (val << hi) {
- val <<= hi;
- ret += hi;
- }
- }
-
- return ret;
-}
-
void glue(helper_pcmpestri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
uint32_t ctrl)
{
@@ -2100,7 +2072,7 @@ void glue(helper_pcmpestri, SUFFIX)(CPUX86State *env, Reg
*d, Reg *s,
pcmp_elen(env, R_EAX, ctrl));
if (res) {
- env->regs[R_ECX] = (ctrl & (1 << 6)) ? rffs1(res) - 1 : 32 - ffs1(res);
+ env->regs[R_ECX] = (ctrl & (1 << 6)) ? 31 - clz32(res) : ctz32(res);
} else {
env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
}
@@ -2138,7 +2110,7 @@ void glue(helper_pcmpistri, SUFFIX)(CPUX86State *env, Reg
*d, Reg *s,
pcmp_ilen(d, ctrl));
if (res) {
- env->regs[R_ECX] = (ctrl & (1 << 6)) ? rffs1(res) - 1 : 32 - ffs1(res);
+ env->regs[R_ECX] = (ctrl & (1 << 6)) ? 31 - clz32(res) : ctz32(res);
} else {
env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
}
--
1.7.10.4
- [Qemu-devel] [PATCH 05/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode, (continued)
- [Qemu-devel] [PATCH 05/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 03/10] target-i386: SSE4.2: fix pcmpXstri instructions, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 04/10] target-i386: SSE4.2: fix pcmpXstrm instructions, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 02/10] target-i386: SSE4.2: fix pcmpgtq instruction, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 09/10] target-i386: enable SSE4.1 and SSE4.2 in TCG mode, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 10/10] target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 06/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" mode, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 01/10] target-i386: SSE4.1: fix pinsrb instruction, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 07/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" mode, Aurelien Jarno, 2013/03/26