Re: [Qemu-devel] [PATCH 03/21] target-mips: add SELEQZ and SELNEZ instructions

[Aurelien Jarno]

On Fri, May 30, 2014 at 03:47:41PM +0100, Leon Alrae wrote:
> Signed-off-by: Leon Alrae <address@hidden>
> ---
>  disas/mips.c            |    8 ++++++++
>  target-mips/translate.c |   16 ++++++++++++++++
>  2 files changed, 24 insertions(+), 0 deletions(-)
> 
> diff --git a/disas/mips.c b/disas/mips.c
> index 2106b57..b950e53 100644
> --- a/disas/mips.c
> +++ b/disas/mips.c
> @@ -521,6 +521,8 @@ struct mips_opcode
>  #define INSN_ISA64                0x00000040
>  #define INSN_ISA32R2              0x00000080
>  #define INSN_ISA64R2              0x00000100
> +#define INSN_ISA32R6              0x00000200
> +#define INSN_ISA64R6              0x00000400
>  
>  /* Masks used for MIPS-defined ASEs.  */
>  #define INSN_ASE_MASK                  0x0000f000
> @@ -585,6 +587,8 @@ struct mips_opcode
>  #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
>  #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
>  
> +#define       ISA_MIPS32R6    (ISA_MIPS32R2 | INSN_ISA32R6)
> +#define       ISA_MIPS64R6    (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
>  
>  /* CPU defines, use instead of hardcoding processor number. Keep this
>     in sync with bfd/archures.c in order for machine selection to work.  */
> @@ -1121,6 +1125,8 @@ extern const int bfd_mips16_num_opcodes;
>  #define I64     INSN_ISA64
>  #define I33  INSN_ISA32R2
>  #define I65  INSN_ISA64R2
> +#define I32R6   INSN_ISA32R6
> +#define I64R6   INSN_ISA64R6
>  
>  /* MIPS64 MIPS-3D ASE support.  */
>  #define I16     INSN_MIPS16
> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>     them first.  The assemblers uses a hash table based on the
>     instruction name anyhow.  */
>  /* name,    args,    match,      mask,       pinfo,                  
> membership */
> +{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, 
> I32R6},
> +{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, 
> I32R6},
>  {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                0,      
>         I4|I32|G3       },
>  {"prefx",   "h,t(b)",        0x4c00000f, 0xfc0007ff, RD_b|RD_t,              
> 0,              I4|I33  },
>  {"nop",     "",         0x00000000, 0xffffffff, 0,                   
> INSN2_ALIAS,    I1      }, /* sll */
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 2ac8023..e5bafae 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -189,6 +189,9 @@ enum {
>      OPC_MOVZ     = 0x0A | OPC_SPECIAL,
>      OPC_MOVN     = 0x0B | OPC_SPECIAL,
>  
> +    OPC_SELEQZ   = 0x35 | OPC_SPECIAL,
> +    OPC_SELNEZ   = 0x37 | OPC_SPECIAL,
> +
>      OPC_MOVCI    = 0x01 | OPC_SPECIAL,
>  
>      /* Special */
> @@ -2406,6 +2409,14 @@ static void gen_cond_move(DisasContext *ctx, uint32_t 
> opc,
>          tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, 
> cpu_gpr[rd]);
>          opn = "movz";
>          break;
> +    case OPC_SELNEZ:
> +        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t1, t2);
> +        opn = "selnez";
> +        break;
> +    case OPC_SELEQZ:
> +        tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t1, t2);
> +        opn = "seleqz";
> +        break;
>      }
>      tcg_temp_free(t2);
>      tcg_temp_free(t1);
> @@ -14480,6 +14491,11 @@ static void decode_opc (CPUMIPSState *env, 
> DisasContext *ctx)
>                                   INSN_LOONGSON2E | INSN_LOONGSON2F);
>              gen_cond_move(ctx, op1, rd, rs, rt);
>              break;
> +        case OPC_SELEQZ:
> +        case OPC_SELNEZ:
> +            check_insn(ctx, ISA_MIPS32R6);
> +            gen_cond_move(ctx, op1, rd, rs, rt);
> +            break;
>          case OPC_ADD ... OPC_SUBU:
>              gen_arith(ctx, op1, rd, rs, rt);
>              break;

Reviewed-by: Aurelien Jarno <address@hidden>


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net