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Re: [Qemu-devel] [PATCH 03/21] target-mips: add SELEQZ and SELNEZ instru
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 03/21] target-mips: add SELEQZ and SELNEZ instructions |
Date: |
Fri, 30 May 2014 09:46:30 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 05/30/2014 07:47 AM, Leon Alrae wrote:
> + case OPC_SELNEZ:
> + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t1, t2);
> + opn = "selnez";
> + break;
I find it easier to reason about these things with conditions that match the
instruction. For instance, SELNEZ is "select if not equal zero", therefore I
expect to find a "not equal zero" in the implementation.
Thus I think
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
is a better way to write this, even though the two forms are functionally
identical.
r~
- [Qemu-devel] [PATCH 00/21] target-mips: add MIPS64R6 Instruction Set support, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 01/21] target-mips: introduce MIPS64R6 ISA and a new generic CPU, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 02/21] target-mips: signal RI Exception on instructions removed in R6, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 04/21] target-mips: move LL and SC instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 03/21] target-mips: add SELEQZ and SELNEZ instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 05/21] target-mips: extract decode_opc_special* from decode_opc, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 08/21] target-mips: move PREF, CACHE, LLD and SCD instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 06/21] target-mips: split decode_opc_special* into *_r6 and *_legacy, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 07/21] target-mips: signal RI Exception on DSP and Loongson instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping, Leon Alrae, 2014/05/30