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[Qemu-devel] [PULL 10/21] char: cadence_uart: Split state struct and typ
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/21] char: cadence_uart: Split state struct and type into header |
Date: |
Mon, 18 May 2015 20:15:10 +0100 |
From: Peter Crosthwaite <address@hidden>
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/cadence_uart.c | 29 +----------------------
include/hw/char/cadence_uart.h | 53 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+), 28 deletions(-)
create mode 100644 include/hw/char/cadence_uart.h
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 4a4d3eb..9d379e5 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -16,9 +16,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "hw/sysbus.h"
-#include "sysemu/char.h"
-#include "qemu/timer.h"
+#include "hw/char/cadence_uart.h"
#ifdef CADENCE_UART_ERR_DEBUG
#define DB_PRINT(...) do { \
@@ -85,8 +83,6 @@
#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
-#define CADENCE_UART_RX_FIFO_SIZE 16
-#define CADENCE_UART_TX_FIFO_SIZE 16
#define UART_INPUT_CLK 50000000
#define R_CR (0x00/4)
@@ -108,29 +104,6 @@
#define R_PWID (0x40/4)
#define R_TTRIG (0x44/4)
-#define CADENCE_UART_R_MAX (0x48/4)
-
-#define TYPE_CADENCE_UART "cadence_uart"
-#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
- TYPE_CADENCE_UART)
-
-typedef struct {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- uint32_t r[CADENCE_UART_R_MAX];
- uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
- uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
- uint32_t rx_wpos;
- uint32_t rx_count;
- uint32_t tx_count;
- uint64_t char_tx_time;
- CharDriverState *chr;
- qemu_irq irq;
- QEMUTimer *fifo_trigger_handle;
-} CadenceUARTState;
static void uart_update_status(CadenceUARTState *s)
{
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
new file mode 100644
index 0000000..6310f52
--- /dev/null
+++ b/include/hw/char/cadence_uart.h
@@ -0,0 +1,53 @@
+/*
+ * Device model for Cadence UART
+ *
+ * Copyright (c) 2010 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (address@hidden)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written by Haibing Ma
+ * M.Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CADENCE_UART_H
+
+#include "hw/sysbus.h"
+#include "sysemu/char.h"
+#include "qemu/timer.h"
+
+#define CADENCE_UART_RX_FIFO_SIZE 16
+#define CADENCE_UART_TX_FIFO_SIZE 16
+
+#define CADENCE_UART_R_MAX (0x48/4)
+
+#define TYPE_CADENCE_UART "cadence_uart"
+#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
+ TYPE_CADENCE_UART)
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t r[CADENCE_UART_R_MAX];
+ uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
+ uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
+ uint32_t rx_wpos;
+ uint32_t rx_count;
+ uint32_t tx_count;
+ uint64_t char_tx_time;
+ CharDriverState *chr;
+ qemu_irq irq;
+ QEMUTimer *fifo_trigger_handle;
+} CadenceUARTState;
+
+#define CADENCE_UART_H
+#endif
--
1.9.1
- [Qemu-devel] [PULL 02/21] target-arm: cpu64: Add support for Cortex-A53, (continued)
- [Qemu-devel] [PULL 02/21] target-arm: cpu64: Add support for Cortex-A53, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 21/21] target-arm: Remove unneeded '+', Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 19/21] target-arm: Correct accessfn for CNTP_{CT}VAL_EL0, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 18/21] target-arm: Add WFx syndrome function, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 17/21] target-arm: Add EL3 and EL2 TCR checking, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 15/21] linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 20/21] target-arm: Correct accessfn for CNTV_TVAL_EL0, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 14/21] arm: xlnx-ep108: Add bootloading, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 12/21] arm: Add xlnx-ep108 machine, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 11/21] arm: xlnx-zynqmp: Add UART support, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 10/21] char: cadence_uart: Split state struct and type into header,
Peter Maydell <=
- [Qemu-devel] [PULL 16/21] target-arm: Add TTBR regime function and use, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 09/21] char: cadence_uart: Clean up variable names, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 13/21] arm: xlnx-ep108: Add external RAM, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 08/21] arm: xlnx-zynqmp: Add GEM support, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 04/21] arm: xlnx-zynqmp: Add GIC, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 01/21] target-arm: cpu64: generalise name of A57 regs, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 05/21] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 06/21] net: cadence_gem: Clean up variable names, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 03/21] arm: Introduce Xilinx ZynqMP SoC, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 07/21] net: cadence_gem: Split state struct and type into header, Peter Maydell, 2015/05/18