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[Qemu-devel] [PULL 13/21] arm: xlnx-ep108: Add external RAM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/21] arm: xlnx-ep108: Add external RAM |
Date: |
Mon, 18 May 2015 20:15:13 +0100 |
From: Peter Crosthwaite <address@hidden>
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/xlnx-ep108.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index 81704bb..46f145b 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -18,11 +18,16 @@
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
+#include "exec/address-spaces.h"
typedef struct XlnxEP108 {
XlnxZynqMPState soc;
+ MemoryRegion ddr_ram;
} XlnxEP108;
+/* Max 2GB RAM */
+#define EP108_MAX_RAM_SIZE 0x80000000ull
+
static void xlnx_ep108_init(MachineState *machine)
{
XlnxEP108 *s = g_new0(XlnxEP108, 1);
@@ -37,6 +42,21 @@ static void xlnx_ep108_init(MachineState *machine)
error_report("%s", error_get_pretty(err));
exit(1);
}
+
+ if (machine->ram_size > EP108_MAX_RAM_SIZE) {
+ error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
+ "reduced to %llx", machine->ram_size, EP108_MAX_RAM_SIZE);
+ machine->ram_size = EP108_MAX_RAM_SIZE;
+ }
+
+ if (machine->ram_size <= 0x08000000) {
+ qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
+ machine->ram_size);
+ }
+
+ memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram",
+ machine->ram_size);
+ memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
}
static QEMUMachine xlnx_ep108_machine = {
--
1.9.1
- [Qemu-devel] [PULL 18/21] target-arm: Add WFx syndrome function, (continued)
- [Qemu-devel] [PULL 18/21] target-arm: Add WFx syndrome function, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 17/21] target-arm: Add EL3 and EL2 TCR checking, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 15/21] linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 20/21] target-arm: Correct accessfn for CNTV_TVAL_EL0, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 14/21] arm: xlnx-ep108: Add bootloading, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 12/21] arm: Add xlnx-ep108 machine, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 11/21] arm: xlnx-zynqmp: Add UART support, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 10/21] char: cadence_uart: Split state struct and type into header, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 16/21] target-arm: Add TTBR regime function and use, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 09/21] char: cadence_uart: Clean up variable names, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 13/21] arm: xlnx-ep108: Add external RAM,
Peter Maydell <=
- [Qemu-devel] [PULL 08/21] arm: xlnx-zynqmp: Add GEM support, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 04/21] arm: xlnx-zynqmp: Add GIC, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 01/21] target-arm: cpu64: generalise name of A57 regs, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 05/21] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 06/21] net: cadence_gem: Clean up variable names, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 03/21] arm: Introduce Xilinx ZynqMP SoC, Peter Maydell, 2015/05/18
- [Qemu-devel] [PULL 07/21] net: cadence_gem: Split state struct and type into header, Peter Maydell, 2015/05/18
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2015/05/19