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[Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2 |
Date: |
Mon, 14 Sep 2015 14:53:11 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 26 ++++++++++++++++++++++++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a7d577b..1b80516 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -386,6 +386,7 @@ typedef struct CPUARMState {
uint64_t c15_ccnt;
uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
uint64_t vpidr_el2; /* Virtualization Processor ID Register */
+ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
} cp15;
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 86900c2..65b9ff5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2477,6 +2477,12 @@ static uint64_t mpidr_read_val(CPUARMState *env)
static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
+ if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
+ return env->cp15.vmpidr_el2;
+ }
return mpidr_read_val(env);
}
@@ -4138,6 +4144,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, v8_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_EL2)) {
+ uint64_t vmpidr_def = mpidr_read_val(env);
ARMCPRegInfo vpidr_regs[] = {
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
@@ -4148,6 +4155,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL2_RW, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
+ { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
+ .resetvalue = vmpidr_def,
+ .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
+ { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
+ .access = PL2_RW,
+ .resetvalue = vmpidr_def,
+ .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vpidr_regs);
@@ -4166,8 +4183,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* register the no_el2 reginfos.
*/
if (arm_feature(env, ARM_FEATURE_EL3)) {
- /* When EL3 exists but not EL2, VPIDR takes the value
- * of MIDR_EL1.
+ /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
+ * of MIDR_EL1 and MPIDR_EL1.
*/
ARMCPRegInfo vpidr_regs[] = {
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
@@ -4175,6 +4192,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
+ { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+ .type = ARM_CP_NO_RAW,
+ .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vpidr_regs);
--
1.9.1
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val(), Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2,
Peter Maydell <=
- [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14