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[Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations |
Date: |
Mon, 14 Sep 2015 14:53:07 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d84f3c9..200b9f2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6370,7 +6370,9 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (arm_el_is_aa64(env, el)) {
va_size = 64;
if (el > 1) {
- tbi = extract64(tcr->raw_tcr, 20, 1);
+ if (mmu_idx != ARMMMUIdx_S2NS) {
+ tbi = extract64(tcr->raw_tcr, 20, 1);
+ }
} else {
if (extract64(address, 55, 1)) {
tbi = extract64(tcr->raw_tcr, 38, 1);
--
1.9.1
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val(), Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations,
Peter Maydell <=
- [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel, Peter Maydell, 2015/09/14