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[Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2 |
Date: |
Mon, 14 Sep 2015 14:53:06 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 34 ++++++++++++++++++++++++++++++++--
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f91b793..96b8f2a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -222,6 +222,7 @@ typedef struct CPUARMState {
};
uint64_t ttbr1_el[4];
};
+ uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
/* MMU translation table base control. */
TCR tcr_el[4];
TCR vtcr_el2; /* Virtualization Translation Control. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b250ed0..d84f3c9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2213,6 +2213,20 @@ static void vmsa_ttbr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
raw_write(env, ri, value);
}
+static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
+ if (raw_read(env, ri) != value) {
+ tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
+ ARMMMUIdx_S2NS, -1);
+ raw_write(env, ri, value);
+ }
+}
+
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_ALIAS,
@@ -3144,6 +3158,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
.type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 6, .crm = 2,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
+ .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -3286,6 +3307,16 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
.access = PL2_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
+ { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 6, .crm = 2,
+ .type = ARM_CP_64BIT | ARM_CP_ALIAS,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
+ .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
+ .writefn = vttbr_write },
+ { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .writefn = vttbr_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
@@ -5791,8 +5822,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env,
ARMMMUIdx mmu_idx,
int ttbrn)
{
if (mmu_idx == ARMMMUIdx_S2NS) {
- /* TODO: return VTTBR_EL2 */
- g_assert_not_reached();
+ return env->cp15.vttbr_el2;
}
if (ttbrn == 0) {
return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
--
1.9.1
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val(), Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2,
Peter Maydell <=
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc, Peter Maydell, 2015/09/14