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[Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value |
Date: |
Mon, 27 Feb 2017 18:04:32 +0000 |
From: Prasad J Pandit <address@hidden>
In SDHCI protocol, the transfer mode register is defined
to be of 6 bits. Mask its value with '0x0037' so that an
invalid value could not be assigned.
Signed-off-by: Prasad J Pandit <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/sd/sdhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index da32b5f..a65c77d 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -119,6 +119,7 @@
(SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
(SDHC_CAPAB_TOCLKFREQ))
+#define MASK_TRNMOD 0x0037
#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
static uint8_t sdhci_slotint(SDHCIState *s)
@@ -1050,7 +1051,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
if (!(s->capareg & SDHC_CAN_DO_DMA)) {
value &= ~SDHC_TRNS_DMA;
}
- MASKED_WRITE(s->trnmod, mask, value);
+ MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);
MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
/* Writing to the upper byte of CMDREG triggers SD command generation
*/
--
2.7.4
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, (continued)
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand(), Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value,
Peter Maydell <=
- [Qemu-devel] [PULL 29/30] hw/arm/exynos: Fix Linux kernel division by zero for PLLs, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 09/30] cputlb: Don't assume do_unassigned_access() never returns, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 14/30] armv7m: Rewrite NVIC to not use any GIC code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 28/30] bcm2835: add sdhost and gpio controllers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 12/30] armv7m: Rename nvic_state to NVICState, Peter Maydell, 2017/02/27
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, no-reply, 2017/02/27
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2017/02/28