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[Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum |
Date: |
Thu, 1 Jun 2017 18:10:12 +0100 |
icc_bpr_write() was not enforcing that writing a value below the
minimum for the BPR should behave as if the BPR was set to the
minimum value. This doesn't make a difference for the secure
BPRs (since we define the minimum for the QEMU implementation
as zero) but did mean we were allowing the NS BPR1 to be set to
0 when 1 should be the lowest value.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
hw/intc/arm_gicv3_cpuif.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index d31eba0..e660b3f 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1388,6 +1388,7 @@ static void icc_bpr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
+ uint64_t minval;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
icv_bpr_write(env, ri, value);
@@ -1415,6 +1416,11 @@ static void icc_bpr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return;
}
+ minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR;
+ if (value < minval) {
+ value = minval;
+ }
+
cs->icc_bpr[grp] = value & 7;
gicv3_cpuif_update(cs);
}
--
2.7.4
- [Qemu-devel] [PULL 07/27] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access(), (continued)
- [Qemu-devel] [PULL 07/27] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access(), Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 05/27] hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 15/27] armv7m: Implement M profile default memory map, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 21/27] aspeed/i2c: handle LAST command under the RX command, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 06/27] target/arm: clear PMUVER field of AA64DFR0 when vPMU=off, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 02/27] load_uboot_image: don't assume a full header read, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 01/27] libvixl: Correct build failures on NetBSD, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 18/27] arm: add MPU support to M profile CPUs, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 26/27] hw/arm/virt-acpi-build: build SLIT when needed, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum,
Peter Maydell <=
- [Qemu-devel] [PULL 25/27] aspeed: add a temp sensor device on I2C bus 3, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFault, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 08/27] arm: Add support for M profile CPUs having different MMU index semantics, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 27/27] hw/arm/virt: fdt: generate distance-map when needed, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 24/27] hw/misc: add a TMP42{1, 2, 3} device model, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 03/27] hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 23/27] aspeed: add some I2C devices to the Aspeed machines, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 22/27] aspeed/i2c: introduce a state machine, Peter Maydell, 2017/06/01