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[Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling |
Date: |
Thu, 1 Jun 2017 18:10:28 +0100 |
From: Cédric Le Goater <address@hidden>
Multiple I2C commands can be fired simultaneously and the controller
execute the commands following these priorities:
(1) Master Start Command
(2) Master Transmit Command
(3) Slave Transmit Command or Master Receive Command
(4) Master Stop Command
The current code is incorrect with respect to the above sequence and
needs to be reworked to handle each individual command.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/i2c/aspeed_i2c.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index ce5b1f0..56a4fdf 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -171,6 +171,7 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr
offset,
static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
{
+ bus->cmd &= ~0xFFFF;
bus->cmd |= value & 0xFFFF;
bus->intr_status = 0;
@@ -182,15 +183,27 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus,
uint64_t value)
bus->intr_status |= I2CD_INTR_TX_ACK;
}
- } else if (bus->cmd & I2CD_M_TX_CMD) {
+ /* START command is also a TX command, as the slave address is
+ * sent on the bus */
+ bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
+
+ /* No slave found */
+ if (!i2c_bus_busy(bus->bus)) {
+ return;
+ }
+ }
+
+ if (bus->cmd & I2CD_M_TX_CMD) {
if (i2c_send(bus->bus, bus->buf)) {
bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
i2c_end_transfer(bus->bus);
} else {
bus->intr_status |= I2CD_INTR_TX_ACK;
}
+ bus->cmd &= ~I2CD_M_TX_CMD;
+ }
- } else if (bus->cmd & I2CD_M_RX_CMD) {
+ if (bus->cmd & I2CD_M_RX_CMD) {
int ret = i2c_recv(bus->bus);
if (ret < 0) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
@@ -199,6 +212,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus,
uint64_t value)
bus->intr_status |= I2CD_INTR_RX_DONE;
}
bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
+ bus->cmd &= ~I2CD_M_RX_CMD;
}
if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
@@ -208,11 +222,8 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus,
uint64_t value)
i2c_end_transfer(bus->bus);
bus->intr_status |= I2CD_INTR_NORMAL_STOP;
}
+ bus->cmd &= ~I2CD_M_STOP_CMD;
}
-
- /* command is handled, reset it and check for interrupts */
- bus->cmd &= ~0xFFFF;
- aspeed_i2c_bus_raise_interrupt(bus);
}
static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
@@ -262,6 +273,7 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr
offset,
}
aspeed_i2c_bus_handle_cmd(bus, value);
+ aspeed_i2c_bus_raise_interrupt(bus);
break;
default:
--
2.7.4
- [Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU, (continued)
- [Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 21/27] aspeed/i2c: handle LAST command under the RX command, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 06/27] target/arm: clear PMUVER field of AA64DFR0 when vPMU=off, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 02/27] load_uboot_image: don't assume a full header read, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 01/27] libvixl: Correct build failures on NetBSD, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 18/27] arm: add MPU support to M profile CPUs, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 26/27] hw/arm/virt-acpi-build: build SLIT when needed, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 25/27] aspeed: add a temp sensor device on I2C bus 3, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFault, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling,
Peter Maydell <=
- [Qemu-devel] [PULL 08/27] arm: Add support for M profile CPUs having different MMU index semantics, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 27/27] hw/arm/virt: fdt: generate distance-map when needed, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 24/27] hw/misc: add a TMP42{1, 2, 3} device model, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 03/27] hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 23/27] aspeed: add some I2C devices to the Aspeed machines, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 22/27] aspeed/i2c: introduce a state machine, Peter Maydell, 2017/06/01