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[Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFau
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFault |
Date: |
Thu, 1 Jun 2017 18:10:25 +0100 |
From: Michael Davidsaver <address@hidden>
General logic is that operations stopped by the MPU are MemManage,
and those which go through the MPU and are caught by the unassigned
handle are BusFault. Distinguish these by looking at the
exception.fsr values, and set the CFSR bits and (if appropriate)
fill in the BFAR or MMFAR with the exception address.
Signed-off-by: Michael Davidsaver <address@hidden>
Message-id: address@hidden
[PMM: i-side faults do not set BFAR/MMFAR, only d-side;
added some CPU_LOG_INT logging]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 180b490..c9d94c5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6342,10 +6342,49 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
- /* TODO: if we implemented the MPU registers, this is where we
- * should set the MMFAR, etc from exception.fsr and exception.vaddress.
+ /* Note that for M profile we don't have a guest facing FSR, but
+ * the env->exception.fsr will be populated by the code that
+ * raises the fault, in the A profile short-descriptor format.
*/
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+ switch (env->exception.fsr & 0xf) {
+ case 0x8: /* External Abort */
+ switch (cs->exception_index) {
+ case EXCP_PREFETCH_ABORT:
+ env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK;
+ qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n");
+ break;
+ case EXCP_DATA_ABORT:
+ env->v7m.cfsr |=
+ (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
+ env->v7m.bfar = env->exception.vaddress;
+ qemu_log_mask(CPU_LOG_INT,
+ "...with CFSR.IBUSERR and BFAR 0x%x\n",
+ env->v7m.bfar);
+ break;
+ }
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
+ break;
+ default:
+ /* All other FSR values are either MPU faults or "can't happen
+ * for M profile" cases.
+ */
+ switch (cs->exception_index) {
+ case EXCP_PREFETCH_ABORT:
+ env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK;
+ qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n");
+ break;
+ case EXCP_DATA_ABORT:
+ env->v7m.cfsr |=
+ (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
+ env->v7m.mmfar = env->exception.vaddress;
+ qemu_log_mask(CPU_LOG_INT,
+ "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
+ env->v7m.mmfar);
+ break;
+ }
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+ break;
+ }
break;
case EXCP_BKPT:
if (semihosting_enabled()) {
--
2.7.4
- [Qemu-devel] [PULL 15/27] armv7m: Implement M profile default memory map, (continued)
- [Qemu-devel] [PULL 15/27] armv7m: Implement M profile default memory map, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 21/27] aspeed/i2c: handle LAST command under the RX command, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 06/27] target/arm: clear PMUVER field of AA64DFR0 when vPMU=off, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 02/27] load_uboot_image: don't assume a full header read, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 01/27] libvixl: Correct build failures on NetBSD, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 18/27] arm: add MPU support to M profile CPUs, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 26/27] hw/arm/virt-acpi-build: build SLIT when needed, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 25/27] aspeed: add a temp sensor device on I2C bus 3, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFault,
Peter Maydell <=
- [Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 08/27] arm: Add support for M profile CPUs having different MMU index semantics, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 27/27] hw/arm/virt: fdt: generate distance-map when needed, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 24/27] hw/misc: add a TMP42{1, 2, 3} device model, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 03/27] hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 23/27] aspeed: add some I2C devices to the Aspeed machines, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 22/27] aspeed/i2c: introduce a state machine, Peter Maydell, 2017/06/01